Lines Matching refs:BUILD_VECTOR
788 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); in X86TargetLowering()
857 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in X86TargetLowering()
879 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); in X86TargetLowering()
880 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); in X86TargetLowering()
1207 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in X86TargetLowering()
1347 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i1, Custom); in X86TargetLowering()
1348 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom); in X86TargetLowering()
1400 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in X86TargetLowering()
1452 setOperationAction(ISD::BUILD_VECTOR, VT, Custom); in X86TargetLowering()
1558 setTargetDAGCombine(ISD::BUILD_VECTOR); in X86TargetLowering()
3953 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); in getZeroVector()
3956 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); in getZeroVector()
3962 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops); in getZeroVector()
3968 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops); in getZeroVector()
3974 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops); in getZeroVector()
3983 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); in getZeroVector()
4014 if (Vec.getOpcode() == ISD::BUILD_VECTOR) in ExtractSubVector()
4015 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT, in ExtractSubVector()
4159 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops); in getOnesVector()
4161 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); in getOnesVector()
4165 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); in getOnesVector()
4291 if (MaskNode->getOpcode() == ISD::BUILD_VECTOR) { in getTargetShuffleMask()
4450 if (V.getOpcode() == ISD::BUILD_VECTOR) in getShuffleScalarElt()
4893 case ISD::BUILD_VECTOR: { in LowerVectorBroadcast()
4924 Sc.getOpcode() != ISD::BUILD_VECTOR) { in LowerVectorBroadcast()
5144 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); in LowerBUILD_VECTORvXi1()
5150 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops); in LowerBUILD_VECTORvXi1()
5804 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, in LowerBUILD_VECTOR()
5806 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, in LowerBUILD_VECTOR()
6212 SDValue V1Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, MaskOps); in lowerVectorShuffleAsBitBlend()
6344 DAG.getNode(ISD::BUILD_VECTOR, DL, BlendVT, VSELECTMask), in lowerVectorShuffleAsBlend()
6586 if (V.getOpcode() != ISD::BUILD_VECTOR || Size != (int)V.getNumOperands()) in computeZeroableShuffleElements()
6633 SDValue VMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, VMaskOps); in lowerVectorShuffleAsBitMask()
6788 DAG.getNode(ISD::BUILD_VECTOR, DL, in lowerVectorShuffleAsSpecificZeroOrAnyExtend()
6925 if (V.getOpcode() == ISD::BUILD_VECTOR || in getScalarValueForVectorElement()
7105 if (V.getOpcode() == ISD::BUILD_VECTOR || in lowerVectorShuffleAsBroadcast()
8298 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V1Mask)); in lowerVectorShuffleAsPSHUFB()
8302 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, V2Mask)); in lowerVectorShuffleAsPSHUFB()
8934 LoV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, LoOps); in splitAndLowerVectorShuffle()
8935 HiV = DAG.getNode(ISD::BUILD_VECTOR, DL, OrigSplitVT, HiOps); in splitAndLowerVectorShuffle()
9560 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask)); in lowerV8F32VectorShuffle()
9565 DAG.getNode(ISD::BUILD_VECTOR, DL, in lowerV8F32VectorShuffle()
9660 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1); in lowerV8I32VectorShuffle()
9762 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask))); in lowerV16I16VectorShuffle()
9850 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, PSHUFBMask)); in lowerV32I8VectorShuffle()
11645 SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, in lowerUINT_TO_FP_vXi32()
11651 SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, in lowerUINT_TO_FP_vXi32()
11658 SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, in lowerUINT_TO_FP_vXi32()
11685 SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask, in lowerUINT_TO_FP_vXi32()
11700 SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT, in lowerUINT_TO_FP_vXi32()
12105 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask); in LowerTRUNCATE()
13054 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1); in ChangeVSETULTtoVSETULE()
13220 SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, in LowerVSETCC()
14587 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts); in getTargetVShiftByConstNode()
14634 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, BVT, ShOps); in getTargetVShiftNode()
16124 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V)); in LowerScalarImmediateShift()
16135 DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V)); in LowerScalarImmediateShift()
16148 SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V); in LowerScalarImmediateShift()
16162 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { in LowerScalarImmediateShift()
16237 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { in LowerScalarVariableShift()
16312 Amt.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) { in LowerScalarVariableShift()
16412 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts); in LowerShift()
16567 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { in LowerShift()
16573 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts); in LowerShift()
16574 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts); in LowerShift()
16904 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts); in LowerBITCAST()
16968 SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones); in LowerCTPOP()
16974 SDValue M55 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask55); in LowerCTPOP()
16985 SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33); in LowerCTPOP()
16987 SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos); in LowerCTPOP()
17006 SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours); in LowerCTPOP()
17011 SDValue M0F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask0F); in LowerCTPOP()
17039 SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts); in LowerCTPOP()
17048 SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV); in LowerCTPOP()
17189 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); in LowerOperation()
17347 SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias); in ReplaceNodeResults()
17487 Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts)); in ReplaceNodeResults()
19465 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || in PerformShuffleCombine256()
19702 DAG.getNode(ISD::BUILD_VECTOR, DL, ByteVT, PSHUFBMask); in combineX86ShuffleChain()
20477 N->getOperand(0)->getOpcode() != ISD::BUILD_VECTOR || in PerformBITCASTCombine()
22128 N1 = DAG.getNode(ISD::BUILD_VECTOR, DL, WideVT, C); in WidenMaskArithmetic()
22174 if (N1.getOpcode() != ISD::BUILD_VECTOR) in VectorZextCombine()
23931 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DAG, Subtarget); in PerformDAGCombine()