Lines Matching refs:FP_TO_SINT
217 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); in X86TargetLowering()
222 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); in X86TargetLowering()
223 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); in X86TargetLowering()
226 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); in X86TargetLowering()
228 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); in X86TargetLowering()
230 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); in X86TargetLowering()
231 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); in X86TargetLowering()
727 setOperationAction(ISD::FP_TO_SINT, VT, Expand); in X86TargetLowering()
919 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); in X86TargetLowering()
1062 setOperationAction(ISD::FP_TO_SINT, MVT::v8i16, Promote); in X86TargetLowering()
1064 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); in X86TargetLowering()
1282 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Legal); in X86TargetLowering()
1288 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Legal); in X86TargetLowering()
1292 setOperationAction(ISD::FP_TO_SINT, MVT::v16i32, Legal); in X86TargetLowering()
16422 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); in LowerShift()
17212 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); in LowerOperation()
17311 case ISD::FP_TO_SINT: in ReplaceNodeResults()
17318 bool IsSigned = N->getOpcode() == ISD::FP_TO_SINT; in ReplaceNodeResults()