3773 bool X86TargetLowering::isExtractSubvectorCheap(EVT ResVT,  in isExtractSubvectorCheap()  argument
3775   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))  in isExtractSubvectorCheap()
3778   return (Index == 0 || Index == ResVT.getVectorNumElements());  in isExtractSubvectorCheap()
5951   MVT ResVT = Op.getSimpleValueType();  in LowerAVXCONCAT_VECTORS()  local
5953   assert((ResVT.is256BitVector() ||  in LowerAVXCONCAT_VECTORS()
5954           ResVT.is512BitVector()) && "Value type must be 256-/512-bit wide");  in LowerAVXCONCAT_VECTORS()
5958   unsigned NumElems = ResVT.getVectorNumElements();  in LowerAVXCONCAT_VECTORS()
5959   if (ResVT.is256BitVector())  in LowerAVXCONCAT_VECTORS()
5960     return Concat128BitVectors(V1, V2, ResVT, NumElems, DAG, dl);  in LowerAVXCONCAT_VECTORS()
5963     MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),  in LowerAVXCONCAT_VECTORS()
5964                                 ResVT.getVectorNumElements()/2);  in LowerAVXCONCAT_VECTORS()
5968       Concat128BitVectors(V3, V4, HalfVT, NumElems/2, DAG, dl), ResVT, NumElems, DAG, dl);  in LowerAVXCONCAT_VECTORS()
5970   return Concat256BitVectors(V1, V2, ResVT, NumElems, DAG, dl);  in LowerAVXCONCAT_VECTORS()
5977   MVT ResVT = Op.getSimpleValueType();  in LowerCONCAT_VECTORSvXi1()  local
5984     MVT HalfVT = MVT::getVectorVT(ResVT.getScalarType(),  in LowerCONCAT_VECTORSvXi1()
5985                                   ResVT.getVectorNumElements()/2);  in LowerCONCAT_VECTORSvXi1()
5994     return DAG.getNode(ISD::CONCAT_VECTORS, dl, ResVT, Lo, Hi);  in LowerCONCAT_VECTORSvXi1()
6003     return getZeroVector(ResVT, Subtarget, DAG, dl);  in LowerCONCAT_VECTORSvXi1()
6006   SDValue Undef = DAG.getUNDEF(ResVT);  in LowerCONCAT_VECTORSvXi1()
6007   unsigned NumElems = ResVT.getVectorNumElements();  in LowerCONCAT_VECTORSvXi1()
6010   V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);  in LowerCONCAT_VECTORSvXi1()
6011   V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);  in LowerCONCAT_VECTORSvXi1()
6015   V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx);  in LowerCONCAT_VECTORSvXi1()
6017   V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits);  in LowerCONCAT_VECTORSvXi1()
6018   V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);  in LowerCONCAT_VECTORSvXi1()
6021   return DAG.getNode(ISD::OR, dl, ResVT, V1, V2);  in LowerCONCAT_VECTORSvXi1()
10756   MVT ResVT   = Op.getSimpleValueType();  in LowerEXTRACT_SUBVECTOR()  local
10760     if (ResVT.is128BitVector() &&  in LowerEXTRACT_SUBVECTOR()
10765     if (ResVT.is256BitVector() && InVT.is512BitVector() &&  in LowerEXTRACT_SUBVECTOR()