6018   V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits);  in LowerCONCAT_VECTORSvXi1()
6693                            : (ByteShift ? X86ISD::VSRLDQ : X86ISD::VSRLI);  in lowerVectorShuffleAsShift()
10445   Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,  in ExtractBitFromMaskVector()
10595   EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,  in InsertBitToMaskVector()
10830       Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);  in LowerINSERT_SUBVECTOR()
10842       Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits);  in LowerINSERT_SUBVECTOR()
10844       Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits);  in LowerINSERT_SUBVECTOR()
14536   assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)  in getTargetVShiftByConstNode()
14561     case X86ISD::VSRLI:  in getTargetVShiftByConstNode()
14610     case X86ISD::VSRLI: Opc = X86ISD::VSRL; break;  in getTargetVShiftNode()
15933   SDValue Ahi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, A, 32, DAG);  in LowerMUL()
15934   SDValue Bhi = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, B, 32, DAG);  in LowerMUL()
16104           return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,  in LowerScalarImmediateShift()
16128           SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT,  in LowerScalarImmediateShift()
16196       return getTargetVShiftByConstNode(X86ISD::VSRLI, dl, VT, R, ShiftAmt,  in LowerScalarImmediateShift()
16301           return getTargetVShiftNode(X86ISD::VSRLI, dl, VT, R, BaseShAmt, DAG);  in LowerScalarVariableShift()
17584   case X86ISD::VSRLI:              return "X86ISD::VSRLI";  in getTargetNodeName()