1244     addRegisterClass(MVT::v16f32, &X86::VR512RegClass);  in X86TargetLowering()
1260     setOperationAction(ISD::LOAD,               MVT::v16f32, Legal);  in X86TargetLowering()
1266     setOperationAction(ISD::FADD,               MVT::v16f32, Legal);  in X86TargetLowering()
1267     setOperationAction(ISD::FSUB,               MVT::v16f32, Legal);  in X86TargetLowering()
1268     setOperationAction(ISD::FMUL,               MVT::v16f32, Legal);  in X86TargetLowering()
1269     setOperationAction(ISD::FDIV,               MVT::v16f32, Legal);  in X86TargetLowering()
1270     setOperationAction(ISD::FSQRT,              MVT::v16f32, Legal);  in X86TargetLowering()
1271     setOperationAction(ISD::FNEG,               MVT::v16f32, Custom);  in X86TargetLowering()
1280     setOperationAction(ISD::FMA,                MVT::v16f32, Legal);  in X86TargetLowering()
1321     setOperationAction(ISD::FFLOOR,             MVT::v16f32, Legal);  in X86TargetLowering()
1323     setOperationAction(ISD::FCEIL,              MVT::v16f32, Legal);  in X86TargetLowering()
1325     setOperationAction(ISD::FTRUNC,             MVT::v16f32, Legal);  in X86TargetLowering()
1327     setOperationAction(ISD::FRINT,              MVT::v16f32, Legal);  in X86TargetLowering()
1329     setOperationAction(ISD::FNEARBYINT,         MVT::v16f32, Legal);  in X86TargetLowering()
1334     setOperationAction(ISD::CONCAT_VECTORS,     MVT::v16f32,  Custom);  in X86TargetLowering()
1351     setOperationAction(ISD::SELECT,             MVT::v16f32, Custom);  in X86TargetLowering()
2552       VecVT = MVT::v16f32;  in LowerFormalArguments()
9953   assert(V1.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");  in lowerV16F32VectorShuffle()
9954   assert(V2.getSimpleValueType() == MVT::v16f32 && "Bad operand type!");  in lowerV16F32VectorShuffle()
9965     return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v16f32, V1, V2);  in lowerV16F32VectorShuffle()
9971     return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v16f32, V1, V2);  in lowerV16F32VectorShuffle()
9974   return splitAndLowerVectorShuffle(DL, MVT::v16f32, V1, V2, Mask, DAG);  in lowerV16F32VectorShuffle()
10086   case MVT::v16f32:  in lower512BitVectorShuffle()
24570       case MVT::v16f32:  in getRegForInlineAsmConstraint()