Lines Matching refs:v16i1
1250 addRegisterClass(MVT::v16i1, &X86::VK16RegClass); in X86TargetLowering()
1264 setOperationAction(ISD::LOAD, MVT::v16i1, Legal); in X86TargetLowering()
1298 setOperationAction(ISD::SINT_TO_FP, MVT::v16i1, Custom); in X86TargetLowering()
1311 setOperationAction(ISD::TRUNCATE, MVT::v16i1, Custom); in X86TargetLowering()
1336 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i1, Legal); in X86TargetLowering()
1338 setOperationAction(ISD::SETCC, MVT::v16i1, Custom); in X86TargetLowering()
1344 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i1, Custom); in X86TargetLowering()
1345 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i1, Custom); in X86TargetLowering()
1348 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i1, Custom); in X86TargetLowering()
1609 case 16: return MVT::v16i1; in getSetCCResultType()
1632 case 16: return MVT::v16i1; in getSetCCResultType()
2346 else if (RegVT == MVT::v16i1) in LowerFormalArguments()
5177 SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, in LowerBUILD_VECTORvXi1()
5198 MVT SelectVT = (VT == MVT::v16i1)? MVT::i16 : MVT::i8; in LowerBUILD_VECTORvXi1()
10441 rc = getRegClassFor(MVT::v16i1); in ExtractBitFromMaskVector()
14981 SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
14982 SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2)); in LowerINTRINSIC_WO_CHAIN()