1245     addRegisterClass(MVT::v8i64,  &X86::VR512RegClass);  in X86TargetLowering()
1262     setOperationAction(ISD::LOAD,               MVT::v8i64, Legal);  in X86TargetLowering()
1314     setOperationAction(ISD::ZERO_EXTEND,        MVT::v8i64, Custom);  in X86TargetLowering()
1316     setOperationAction(ISD::SIGN_EXTEND,        MVT::v8i64, Custom);  in X86TargetLowering()
1333     setOperationAction(ISD::CONCAT_VECTORS,     MVT::v8i64,  Custom);  in X86TargetLowering()
1341     setOperationAction(ISD::MUL,              MVT::v8i64, Custom);  in X86TargetLowering()
1350     setOperationAction(ISD::SELECT,             MVT::v8i64, Custom);  in X86TargetLowering()
1353     setOperationAction(ISD::ADD,                MVT::v8i64, Legal);  in X86TargetLowering()
1356     setOperationAction(ISD::SUB,                MVT::v8i64, Legal);  in X86TargetLowering()
1361     setOperationAction(ISD::SRL,                MVT::v8i64, Custom);  in X86TargetLowering()
1364     setOperationAction(ISD::SHL,                MVT::v8i64, Custom);  in X86TargetLowering()
1367     setOperationAction(ISD::SRA,                MVT::v8i64, Custom);  in X86TargetLowering()
1370     setOperationAction(ISD::AND,                MVT::v8i64, Legal);  in X86TargetLowering()
1371     setOperationAction(ISD::OR,                 MVT::v8i64, Legal);  in X86TargetLowering()
1372     setOperationAction(ISD::XOR,                MVT::v8i64, Legal);  in X86TargetLowering()
1378       setOperationAction(ISD::CTLZ,             MVT::v8i64, Legal);  in X86TargetLowering()
1409     for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {  in X86TargetLowering()
1417       AddPromotedToType (ISD::SELECT, VT, MVT::v8i64);  in X86TargetLowering()
1442     for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {  in X86TargetLowering()
9982   assert(V1.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");  in lowerV8I64VectorShuffle()
9983   assert(V2.getSimpleValueType() == MVT::v8i64 && "Bad operand type!");  in lowerV8I64VectorShuffle()
9991     return DAG.getNode(X86ISD::UNPCKL, DL, MVT::v8i64, V1, V2);  in lowerV8I64VectorShuffle()
9993     return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v8i64, V1, V2);  in lowerV8I64VectorShuffle()
9996   return splitAndLowerVectorShuffle(DL, MVT::v8i64, V1, V2, Mask, DAG);  in lowerV8I64VectorShuffle()
10088   case MVT::v8i64:  in lower512BitVectorShuffle()
10431     MVT ExtVT = (VecVT == MVT::v8i1 ?  MVT::v8i64 : MVT::v16i32);  in ExtractBitFromMaskVector()
10578     MVT ExtVecVT = (VecVT == MVT::v8i1 ?  MVT::v8i64 : MVT::v16i32);  in InsertBitToMaskVector()
11974   EVT ExtVT = (NumElts == 8)? MVT::v8i64 : MVT::v16i32;  in LowerZERO_EXTEND_AVX512()
12049       MVT ExtVT = (NumElts == 16)? MVT::v16i32 : MVT::v8i64;  in LowerTRUNCATE()
13695   MVT ExtVT = (NumElts == 8) ? MVT::v8i64 : MVT::v16i32;  in LowerSIGN_EXTEND_AVX512()
15919   assert((VT == MVT::v2i64 || VT == MVT::v4i64 || VT == MVT::v8i64) &&  in LowerMUL()
16099            (VT == MVT::v8i64 || VT == MVT::v16i32))) {  in LowerScalarImmediateShift()
16219        (Subtarget->hasAVX512() && (VT == MVT::v8i64 || VT == MVT::v16i32))) {  in LowerScalarVariableShift()
16276         case MVT::v8i64:  in LowerScalarVariableShift()
16287         case MVT::v8i64:  in LowerScalarVariableShift()
16300         case MVT::v8i64:  in LowerScalarVariableShift()
16310       (Subtarget->hasAVX512() && VT == MVT::v8i64)) &&  in LowerScalarVariableShift()
16355   if (Subtarget->hasAVX512() && (VT == MVT::v16i32 || VT == MVT::v8i64))  in LowerShift()
20650   case MVT::v8i64:  in matchIntegerMINMAX()
24572       case MVT::v8i64:  in getRegForInlineAsmConstraint()