Lines Matching refs:WriteRes

81   def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
85   def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
94   def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
98   def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
104 def : WriteRes<WriteRMW, [JSAGU]>;
113 def  : WriteRes<WriteIMulH, [JALU1]> {
119 def : WriteRes<WriteIDiv, [JALU1, JDiv]> {
123 def : WriteRes<WriteIDivLd, [JALU1, JLAGU, JDiv]> {
130 def : WriteRes<WriteLEA, [JALU01]>;
143 def : WriteRes<WriteLoad,  [JLAGU]> { let Latency = 5; }
144 def : WriteRes<WriteStore, [JSAGU]>;
145 def : WriteRes<WriteMove,  [JAny]>;
152 def : WriteRes<WriteZero,  []>;
177 def : WriteRes<WriteFSqrt, [JFPU1, JLAGU, JFPM]> {
181 def : WriteRes<WriteFSqrtLd, [JFPU1, JLAGU, JFPM]> {
186 def : WriteRes<WriteFDiv, [JFPU1, JLAGU, JFPM]> {
190 def : WriteRes<WriteFDivLd, [JFPU1, JLAGU, JFPM]> {
200 def : WriteRes<WriteFVarBlend, [JFPU01]> {
204 def : WriteRes<WriteFVarBlendLd, [JLAGU, JFPU01]> {
218 def : WriteRes<WriteVarBlend, [JFPU01]> {
222 def : WriteRes<WriteVarBlendLd, [JLAGU, JFPU01]> {
228 def : WriteRes<WriteVarVecShift, [JFPU01]> {
232 def : WriteRes<WriteVarVecShiftLd, [JLAGU, JFPU01]> {
237 def : WriteRes<WriteMPSAD, [JFPU0]> {
241 def : WriteRes<WriteMPSADLd, [JLAGU, JFPU0]> {
252 def : WriteRes<WritePCmpIStrM, [JFPU01]> {
256 def : WriteRes<WritePCmpIStrMLd, [JLAGU, JFPU01]> {
262 def : WriteRes<WritePCmpEStrM, [JFPU01]> {
266 def : WriteRes<WritePCmpEStrMLd, [JLAGU, JFPU01]> {
272 def : WriteRes<WritePCmpIStrI, [JFPU01]> {
276 def : WriteRes<WritePCmpIStrILd, [JLAGU, JFPU01]> {
282 def : WriteRes<WritePCmpEStrI, [JFPU01]> {
286 def : WriteRes<WritePCmpEStrILd, [JLAGU, JFPU01]> {
295 def : WriteRes<WriteAESDecEnc, [JFPU01, JVIMUL]> {
299 def : WriteRes<WriteAESDecEncLd, [JFPU01, JLAGU, JVIMUL]> {
304 def : WriteRes<WriteAESIMC, [JVIMUL]> {
308 def : WriteRes<WriteAESIMCLd, [JLAGU, JVIMUL]> {
313 def : WriteRes<WriteAESKeyGen, [JVIMUL]> {
317 def : WriteRes<WriteAESKeyGenLd, [JLAGU, JVIMUL]> {
326 def : WriteRes<WriteCLMul, [JVIMUL]> {
330 def : WriteRes<WriteCLMulLd, [JLAGU, JVIMUL]> {
336 def : WriteRes<WriteSystem,     [JAny]> { let Latency = 100; }
337 def : WriteRes<WriteMicrocoded, [JAny]> { let Latency = 100; }
338 def : WriteRes<WriteFence,  [JSAGU]>;
339 def : WriteRes<WriteNop, []>;