Lines Matching refs:WriteRes

63   def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
67   def : WriteRes<SchedRW.Folded, [MEC_RSV, ExePort]> {
74 def : WriteRes<WriteRMW, [MEC_RSV]>;
76 def : WriteRes<WriteStore, [IEC_RSV01, MEC_RSV]>;
77 def : WriteRes<WriteLoad,  [MEC_RSV]> { let Latency = 3; }
78 def : WriteRes<WriteMove,  [IEC_RSV01]>;
79 def : WriteRes<WriteZero,  []>;
89 def : WriteRes<WriteLEA, [IEC_RSV1]>;
92 def : WriteRes<WriteIDiv, [IEC_RSV01, SMDivider]> {
96 def : WriteRes<WriteIDivLd, [MEC_RSV, IEC_RSV01, SMDivider]> {
113 def : WriteRes<WriteFMul, [FPC_RSV0, SMFPMultiplier]> {
117 def : WriteRes<WriteFMulLd, [MEC_RSV, FPC_RSV0, SMFPMultiplier]> {
122 def : WriteRes<WriteFDiv, [FPC_RSV0, SMFPDivider]> {
126 def : WriteRes<WriteFDivLd, [MEC_RSV, FPC_RSV0, SMFPDivider]> {
142 def : WriteRes<WritePCmpIStrM, [FPC_RSV0]> {
146 def : WriteRes<WritePCmpIStrMLd, [FPC_RSV0, MEC_RSV]> {
152 def : WriteRes<WritePCmpEStrM, [FPC_RSV0]> {
156 def : WriteRes<WritePCmpEStrMLd, [FPC_RSV0, MEC_RSV]> {
162 def : WriteRes<WritePCmpIStrI, [FPC_RSV0]> {
166 def : WriteRes<WritePCmpIStrILd, [FPC_RSV0, MEC_RSV]> {
172 def : WriteRes<WritePCmpEStrI, [FPC_RSV0]> {
176 def : WriteRes<WritePCmpEStrILd, [FPC_RSV0, MEC_RSV]> {
182 def : WriteRes<WriteAESDecEnc, [FPC_RSV0]> {
186 def : WriteRes<WriteAESDecEncLd, [FPC_RSV0, MEC_RSV]> {
191 def : WriteRes<WriteAESIMC, [FPC_RSV0]> {
195 def : WriteRes<WriteAESIMCLd, [FPC_RSV0, MEC_RSV]> {
200 def : WriteRes<WriteAESKeyGen, [FPC_RSV0]> {
204 def : WriteRes<WriteAESKeyGenLd, [FPC_RSV0, MEC_RSV]> {
210 def : WriteRes<WriteCLMul, [FPC_RSV0]> {
214 def : WriteRes<WriteCLMulLd, [FPC_RSV0, MEC_RSV]> {
220 def : WriteRes<WriteSystem,     [FPC_RSV0]> { let Latency = 100; }
221 def : WriteRes<WriteMicrocoded, [FPC_RSV0]> { let Latency = 100; }
222 def : WriteRes<WriteFence, [MEC_RSV]>;
223 def : WriteRes<WriteNop, []>;
227 def  : WriteRes<WriteIMulH, [FPC_RSV0]>;