Lines Matching refs:smaxv
47 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32>)
49 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16>)
51 declare i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8>)
57 declare i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16>)
59 declare i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8>)
167 ; CHECK: smaxv b{{[0-9]+}}, {{v[0-9]+}}.8b
169 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i8(<8 x i8> %a)
170 %0 = trunc i32 %smaxv.i to i8
176 ; CHECK: smaxv h{{[0-9]+}}, {{v[0-9]+}}.4h
178 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i16(<4 x i16> %a)
179 %0 = trunc i32 %smaxv.i to i16
203 ; CHECK: smaxv b{{[0-9]+}}, {{v[0-9]+}}.16b
205 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v16i8(<16 x i8> %a)
206 %0 = trunc i32 %smaxv.i to i8
212 ; CHECK: smaxv h{{[0-9]+}}, {{v[0-9]+}}.8h
214 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v8i16(<8 x i16> %a)
215 %0 = trunc i32 %smaxv.i to i16
221 ; CHECK: smaxv s{{[0-9]+}}, {{v[0-9]+}}.4s
223 %smaxv.i = tail call i32 @llvm.aarch64.neon.smaxv.i32.v4i32(<4 x i32> %a)
224 ret i32 %smaxv.i