Lines Matching refs:sminv
27 declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)
29 declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)
31 declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)
37 declare i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16>)
39 declare i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8>)
255 ; CHECK: sminv b{{[0-9]+}}, {{v[0-9]+}}.8b
257 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a)
258 %0 = trunc i32 %sminv.i to i8
264 ; CHECK: sminv h{{[0-9]+}}, {{v[0-9]+}}.4h
266 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a)
267 %0 = trunc i32 %sminv.i to i16
291 ; CHECK: sminv b{{[0-9]+}}, {{v[0-9]+}}.16b
293 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a)
294 %0 = trunc i32 %sminv.i to i8
300 ; CHECK: sminv h{{[0-9]+}}, {{v[0-9]+}}.8h
302 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a)
303 %0 = trunc i32 %sminv.i to i16
309 ; CHECK: sminv s{{[0-9]+}}, {{v[0-9]+}}.4s
311 %sminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a)
312 ret i32 %sminv.i