Lines Matching refs:umaxv
41 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>)
43 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>)
45 declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>)
53 declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>)
55 declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>)
185 ; CHECK: umaxv b{{[0-9]+}}, {{v[0-9]+}}.8b
187 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a)
188 %0 = trunc i32 %umaxv.i to i8
194 ; CHECK: umaxv h{{[0-9]+}}, {{v[0-9]+}}.4h
196 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a)
197 %0 = trunc i32 %umaxv.i to i16
229 ; CHECK: umaxv b{{[0-9]+}}, {{v[0-9]+}}.16b
231 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a)
232 %0 = trunc i32 %umaxv.i to i8
238 ; CHECK: umaxv h{{[0-9]+}}, {{v[0-9]+}}.8h
240 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a)
241 %0 = trunc i32 %umaxv.i to i16
247 ; CHECK: umaxv s{{[0-9]+}}, {{v[0-9]+}}.4s
249 %umaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a)
250 ret i32 %umaxv.i