Lines Matching refs:half
3 define <4 x i16> @v4f16_to_v4i16(float, <4 x half> %a) #0 {
7 %1 = bitcast <4 x half> %a to <4 x i16>
11 define <2 x i32> @v4f16_to_v2i32(float, <4 x half> %a) #0 {
15 %1 = bitcast <4 x half> %a to <2 x i32>
19 define <1 x i64> @v4f16_to_v1i64(float, <4 x half> %a) #0 {
23 %1 = bitcast <4 x half> %a to <1 x i64>
27 define i64 @v4f16_to_i64(float, <4 x half> %a) #0 {
31 %1 = bitcast <4 x half> %a to i64
35 define <2 x float> @v4f16_to_v2float(float, <4 x half> %a) #0 {
39 %1 = bitcast <4 x half> %a to <2 x float>
43 define <1 x double> @v4f16_to_v1double(float, <4 x half> %a) #0 {
47 %1 = bitcast <4 x half> %a to <1 x double>
51 define double @v4f16_to_double(float, <4 x half> %a) #0 {
55 %1 = bitcast <4 x half> %a to double
60 define <4 x half> @v4i16_to_v4f16(float, <4 x i16> %a) #0 {
64 %1 = bitcast <4 x i16> %a to <4 x half>
65 ret <4 x half> %1
68 define <4 x half> @v2i32_to_v4f16(float, <2 x i32> %a) #0 {
72 %1 = bitcast <2 x i32> %a to <4 x half>
73 ret <4 x half> %1
76 define <4 x half> @v1i64_to_v4f16(float, <1 x i64> %a) #0 {
80 %1 = bitcast <1 x i64> %a to <4 x half>
81 ret <4 x half> %1
84 define <4 x half> @i64_to_v4f16(float, i64 %a) #0 {
88 %1 = bitcast i64 %a to <4 x half>
89 ret <4 x half> %1
92 define <4 x half> @v2float_to_v4f16(float, <2 x float> %a) #0 {
96 %1 = bitcast <2 x float> %a to <4 x half>
97 ret <4 x half> %1
100 define <4 x half> @v1double_to_v4f16(float, <1 x double> %a) #0 {
104 %1 = bitcast <1 x double> %a to <4 x half>
105 ret <4 x half> %1
108 define <4 x half> @double_to_v4f16(float, double %a) #0 {
112 %1 = bitcast double %a to <4 x half>
113 ret <4 x half> %1
125 define <8 x i16> @v8f16_to_v8i16(float, <8 x half> %a) #0 {
129 %1 = bitcast <8 x half> %a to <8 x i16>
133 define <4 x i32> @v8f16_to_v4i32(float, <8 x half> %a) #0 {
137 %1 = bitcast <8 x half> %a to <4 x i32>
141 define <2 x i64> @v8f16_to_v2i64(float, <8 x half> %a) #0 {
145 %1 = bitcast <8 x half> %a to <2 x i64>
149 define <4 x float> @v8f16_to_v4float(float, <8 x half> %a) #0 {
153 %1 = bitcast <8 x half> %a to <4 x float>
157 define <2 x double> @v8f16_to_v2double(float, <8 x half> %a) #0 {
161 %1 = bitcast <8 x half> %a to <2 x double>
165 define <8 x half> @v8i16_to_v8f16(float, <8 x i16> %a) #0 {
169 %1 = bitcast <8 x i16> %a to <8 x half>
170 ret <8 x half> %1
173 define <8 x half> @v4i32_to_v8f16(float, <4 x i32> %a) #0 {
177 %1 = bitcast <4 x i32> %a to <8 x half>
178 ret <8 x half> %1
181 define <8 x half> @v2i64_to_v8f16(float, <2 x i64> %a) #0 {
185 %1 = bitcast <2 x i64> %a to <8 x half>
186 ret <8 x half> %1
189 define <8 x half> @v4float_to_v8f16(float, <4 x float> %a) #0 {
193 %1 = bitcast <4 x float> %a to <8 x half>
194 ret <8 x half> %1
197 define <8 x half> @v2double_to_v8f16(float, <2 x double> %a) #0 {
201 %1 = bitcast <2 x double> %a to <8 x half>
202 ret <8 x half> %1