Lines Matching refs:hexagon

1 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLW
2 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRW
3 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRW
4 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASLH
5 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-ASRH
6 ; RUN: llc -march=hexagon < %s | FileCheck %s --check-prefix=CHECK-LSRH
17 target triple = "hexagon"
21   %0 = tail call i64 @llvm.hexagon.S2.asl.i.vw(i64 %x, i32 9)
22   %1 = tail call i64 @llvm.hexagon.S2.asr.i.vw(i64 %x, i32 8)
23   %2 = tail call i64 @llvm.hexagon.S2.lsr.i.vw(i64 %x, i32 7)
24   %3 = tail call i64 @llvm.hexagon.S2.asl.i.vh(i64 %x, i32 6)
25   %4 = tail call i64 @llvm.hexagon.S2.asr.i.vh(i64 %x, i32 5)
26   %5 = tail call i64 @llvm.hexagon.S2.lsr.i.vh(i64 %x, i32 4)
35 declare i64 @llvm.hexagon.S2.asl.i.vw(i64, i32) nounwind readnone
36 declare i64 @llvm.hexagon.S2.asr.i.vw(i64, i32) nounwind readnone
37 declare i64 @llvm.hexagon.S2.lsr.i.vw(i64, i32) nounwind readnone
38 declare i64 @llvm.hexagon.S2.asl.i.vh(i64, i32) nounwind readnone
39 declare i64 @llvm.hexagon.S2.asr.i.vh(i64, i32) nounwind readnone
40 declare i64 @llvm.hexagon.S2.lsr.i.vh(i64, i32) nounwind readnone