Lines Matching refs:addv
420 %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
425 declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>) nounwind
432 ; CHECK-DAG: addv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]
445 %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %1)
450 declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>) nounwind
457 ; CHECK-DAG: addv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]
470 %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1)
475 declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>) nounwind
482 ; CHECK-DAG: addv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]
495 %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %1)
500 declare <2 x i64> @llvm.mips.addv.d(<2 x i64>, <2 x i64>) nounwind
507 ; CHECK-DAG: addv.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]
527 ; CHECK-DAG: addv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]
547 ; CHECK-DAG: addv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]
567 ; CHECK-DAG: addv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]
587 ; CHECK-DAG: addv.d [[WD:\$w[0-9]+]], [[WS]], [[WT]]