Lines Matching refs:Must
15 ANDS r0, r2, r1 // Must be wide - 3 distinct registers
20 AND r0, r1, r0 // Must use wide encoding as not flag-setting
27 ANDS r2, r2, r1, lsl #1 // Must use wide - shifted register
45 ANDEQ r0, r2, r1 // Must be wide - 3 distinct registers
55 ANDSEQ r0, r1, r0 // Must use wide encoding as flag-setting
69 ANDEQ r0, r0, r1, lsl #1 // Must use wide - shifted register
102 EORS r0, r2, r1 // Must be wide - 3 distinct registers
107 EOR r1, r1, r1 // Must use wide encoding as not flag-setting
114 EORS r2, r2, r1, lsl #1 // Must use wide - shifted register
132 EOREQ r3, r2, r1 // Must be wide - 3 distinct registers
142 EORSEQ r1, r1, r1 // Must use wide encoding as flag-setting
156 EOREQ r4, r4, r1, lsl #1 // Must use wide - shifted register
189 LSLS r0, r2, r1 // Must be wide - 3 distinct registers
194 LSL r4, r1, r4 // Must use wide encoding as not flag-setting
213 LSLEQ r0, r2, r1 // Must be wide - 3 distinct registers
223 LSLSEQ r4, r1, r4 // Must use wide encoding as flag-setting
258 LSRS r6, r2, r1 // Must be wide - 3 distinct registers
263 LSR r4, r1, r4 // Must use wide encoding as not flag-setting
282 LSREQ r6, r2, r1 // Must be wide - 3 distinct registers
292 LSRSEQ r0, r1, r0 // Must use wide encoding as flag-setting
327 ASRS r7, r6, r5 // Must be wide - 3 distinct registers
332 ASR r0, r1, r0 // Must use wide encoding as not flag-setting
351 ASREQ r0, r2, r1 // Must be wide - 3 distinct registers
361 ASRSEQ r3, r1, r3 // Must use wide encoding as flag-setting
396 ADCS r5, r2, r1 // Must be wide - 3 distinct registers
401 ADC r0, r1, r0 // Must use wide encoding as not flag-setting
408 ADCS r3, r3, r1, lsl #1 // Must use wide - shifted register
426 ADCEQ r1, r2, r3 // Must be wide - 3 distinct registers
436 ADCSEQ r3, r1, r3 // Must use wide encoding as flag-setting
450 ADCEQ r2, r2, r1, lsl #1 // Must use wide - shifted register
483 SBCS r3, r2, r1 // Must be wide - 3 distinct registers
488 SBC r0, r1, r0 // Must use wide encoding as not flag-setting
494 SBCS r2, r2, r1, lsl #1 // Must use wide - shifted register
511 SBCEQ r5, r2, r1 // Must be wide - 3 distinct registers
521 SBCSEQ r2, r1, r2 // Must use wide encoding as flag-setting
533 SBCEQ r2, r2, r1, lsl #1 // Must use wide - shifted register
564 RORS r3, r2, r1 // Must be wide - 3 distinct registers
569 ROR r5, r1, r5 // Must use wide encoding as not flag-setting
588 ROREQ r4, r2, r1 // Must be wide - 3 distinct registers
598 RORSEQ r0, r1, r0 // Must use wide encoding as flag-setting
638 ORRS r7, r2, r1 // Must be wide - 3 distinct registers
643 ORR r2, r1, r2 // Must use wide encoding as not flag-setting
650 ORRS r1, r1, r1, lsl #1 // Must use wide - shifted register
668 ORREQ r0, r2, r1 // Must be wide - 3 distinct registers
678 ORRSEQ r4, r1, r4 // Must use wide encoding as flag-setting
692 ORREQ r2, r2, r1, lsl #1 // Must use wide - shifted register
727 BICS r3, r2, r1 // Must be wide - 3 distinct registers
732 BIC r0, r1, r0 // Must use wide encoding as not flag-setting
738 BICS r3, r3, r1, lsl #1 // Must use wide - shifted register
755 BICEQ r0, r2, r1 // Must be wide - 3 distinct registers
765 BICSEQ r5, r1, r5 // Must use wide encoding as flag-setting
777 BICEQ r4, r4, r1, lsl #1 // Must use wide - shifted register