Lines Matching refs:RC
116 for (const auto &RC : RegisterClasses) in runEnums() local
117 OS << " " << RC.getName() << "RegClassID" in runEnums()
118 << " = " << RC.EnumValue << ",\n"; in runEnums()
182 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
183 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure()
188 RC.buildRegUnitSet(RegUnits); in EmitRegUnitPressure()
192 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
957 for (const auto &RC : RegisterClasses) { in runMCDesc() local
958 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc()
961 std::string Name = RC.getName(); in runMCDesc()
997 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1000 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large."); in runMCDesc()
1001 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large."); in runMCDesc()
1002 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large."); in runMCDesc()
1004 OS << " { " << RC.getName() << ", " << RC.getName() << "Bits, " in runMCDesc()
1005 << RegClassStrings.get(RC.getName()) << ", " in runMCDesc()
1006 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), " in runMCDesc()
1007 << RC.getQualifiedName() + "RegClassID" << ", " in runMCDesc()
1008 << RC.SpillSize/8 << ", " in runMCDesc()
1009 << RC.SpillAlignment/8 << ", " in runMCDesc()
1010 << RC.CopyCost << ", " in runMCDesc()
1011 << RC.Allocatable << " },\n"; in runMCDesc()
1105 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1106 const std::string &Name = RC.getName(); in runTargetHeader()
1142 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1143 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc()
1145 if (RC.Allocatable) in runTargetDesc()
1151 for (const auto &RC : RegisterClasses) in runTargetDesc() local
1152 VTSeqs.add(RC.VTs); in runTargetDesc()
1205 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1206 OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; in runTargetDesc()
1207 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1211 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; in runTargetDesc()
1214 RC.getSuperRegClasses(&Idx, MaskBV); in runTargetDesc()
1232 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1233 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); in runTargetDesc()
1240 << RC.getName() << "Superclasses[] = {\n"; in runTargetDesc()
1247 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1248 if (!RC.AltOrderSelect.empty()) { in runTargetDesc()
1249 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1251 << RC.AltOrderSelect << "}\n\n" in runTargetDesc()
1252 << "static ArrayRef<MCPhysReg> " << RC.getName() in runTargetDesc()
1254 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { in runTargetDesc()
1255 ArrayRef<Record*> Elems = RC.getOrder(oi); in runTargetDesc()
1264 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" in runTargetDesc()
1267 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) in runTargetDesc()
1268 if (RC.getOrder(oi).empty()) in runTargetDesc()
1272 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1273 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() in runTargetDesc()
1282 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1283 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1285 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " in runTargetDesc()
1286 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " << RC.getName() in runTargetDesc()
1288 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n " in runTargetDesc()
1289 << format("0x%08x,\n ", RC.LaneMask) in runTargetDesc()
1290 << (unsigned)RC.AllocationPriority << ",\n " in runTargetDesc()
1291 << (RC.HasDisjunctSubRegs?"true":"false") in runTargetDesc()
1293 if (RC.getSuperClasses().empty()) in runTargetDesc()
1296 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1297 if (RC.AltOrderSelect.empty()) in runTargetDesc()
1300 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1309 for (const auto &RC : RegisterClasses) in runTargetDesc() local
1310 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1353 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1354 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1356 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) in runTargetDesc()