56   void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
59                             const std::deque<CodeGenRegister> &Regs,
183     const CodeGenRegister::Vec &Regs = RC.getMembers();  in EmitRegUnitPressure()  local
184     if (Regs.empty())  in EmitRegUnitPressure()
189       OS << "    {" << (*Regs.begin())->getWeight(RegBank)  in EmitRegUnitPressure()
321     raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {  in EmitRegMappingTables()  argument
328   for (auto &RE : Regs) {  in EmitRegMappingTables()
347   std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");  in EmitRegMappingTables()
395   for (auto &RE : Regs) {  in EmitRegMappingTables()
444     raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) {  in EmitRegMapping()  argument
448   for (auto &RE : Regs) {  in EmitRegMapping()
457   std::string Namespace = Regs.front().TheDef->getValueAsString("Namespace");  in EmitRegMapping()
790   const auto &Regs = RegBank.getRegisters();  in runMCDesc()  local
799   SmallVector<DiffVec, 4> SubRegLists(Regs.size());  in runMCDesc()
800   SmallVector<DiffVec, 4> SuperRegLists(Regs.size());  in runMCDesc()
801   SmallVector<DiffVec, 4> RegUnitLists(Regs.size());  in runMCDesc()
802   SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());  in runMCDesc()
806   SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size());  in runMCDesc()
812   SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size());  in runMCDesc()
818   for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) {  in runMCDesc()
853     if (I != Regs.begin() &&  in runMCDesc()
856     if (std::next(I) != Regs.end() &&  in runMCDesc()
925   for (const auto &Reg : Regs) {  in runMCDesc()
1016   EmitRegMappingTables(OS, Regs, false);  in runMCDesc()
1023   for (const auto &RE : Regs) {  in runMCDesc()
1041      << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "  in runMCDesc()
1050   EmitRegMapping(OS, Regs, false);  in runMCDesc()
1320   const auto &Regs = RegBank.getRegisters();  in runTargetDesc()  local
1321   for (const auto &Reg : Regs) {  in runTargetDesc()
1385   EmitRegMappingTables(OS, Regs, true);  in runTargetDesc()
1394      << "  InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1  in runTargetDesc()
1408   EmitRegMapping(OS, Regs, true);  in runTargetDesc()
1418     const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);  in runTargetDesc()  local
1419     assert(Regs && "Cannot expand CalleeSavedRegs instance");  in runTargetDesc()
1424     for (unsigned r = 0, re = Regs->size(); r != re; ++r)  in runTargetDesc()
1425       OS << getQualifiedName((*Regs)[r]) << ", ";  in runTargetDesc()
1429     BitVector Covered = RegBank.computeCoveredRegisters(*Regs);  in runTargetDesc()