Lines Matching refs:ModelDef
673 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindWriteResources() local
674 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindWriteResources()
705 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindWriteResources()
727 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel"); in FindReadAdvance() local
728 if (&SchedModels.getProcModel(ModelDef) != &ProcModel) in FindReadAdvance()
759 PrintFatalError(ProcModel.ModelDef->getLoc(), in FindReadAdvance()
1178 PrintFatalError(PI->ModelDef->getLoc(), "SchedMachineModel defines " in EmitProcessorModels()
1184 EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ','); in EmitProcessorModels()
1185 EmitProcessorProp(OS, PI->ModelDef, "MicroOpBufferSize", ','); in EmitProcessorModels()
1186 EmitProcessorProp(OS, PI->ModelDef, "LoopMicroOpBufferSize", ','); in EmitProcessorModels()
1187 EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ','); in EmitProcessorModels()
1188 EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ','); in EmitProcessorModels()
1189 EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ','); in EmitProcessorModels()
1191 OS << " " << (bool)(PI->ModelDef ? in EmitProcessorModels()
1192 PI->ModelDef->getValueAsBit("PostRAScheduler") : 0) in EmitProcessorModels()
1195 OS << " " << (bool)(PI->ModelDef ? in EmitProcessorModels()
1196 PI->ModelDef->getValueAsBit("CompleteModel") : 0) in EmitProcessorModels()