Lines Matching refs:getValueAsListOfDefs

195       Feature->getValueAsListOfDefs("Implies");  in FeatureKeyValues()
243       Processor->getValueAsListOfDefs("Features");  in CPUKeyValues()
285     ItinData->getValueAsListOfDefs("Stages");  in FormItineraryStageString()
298     const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");  in FormItineraryStageString()
346     ItinData->getValueAsListOfDefs("Bypasses");  in FormItineraryBypassString()
379     std::vector<Record*> FUs = PI->ItinsDef->getValueAsListOfDefs("FU");  in EmitStageAndOperandCycleData()
393     std::vector<Record*> BPs = PI->ItinsDef->getValueAsListOfDefs("BP");  in EmitStageAndOperandCycleData()
627       RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");  in EmitProcessorResources()
777       SubResources = PRDef->getValueAsListOfDefs("Resources");  in ExpandProcResources()
800       RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources");  in ExpandProcResources()
887         SchedModels.findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),  in GenSchedClassTables()
895         RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");  in GenSchedClassTables()
898           SchedModels.findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"),  in GenSchedClassTables()
948         RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");  in GenSchedClassTables()
992       RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites");  in GenSchedClassTables()