Lines Matching full:info
104 nvc0_vp_assign_input_slots(struct nv50_ir_prog_info *info) in nvc0_vp_assign_input_slots() argument
108 for (n = 0, i = 0; i < info->numInputs; ++i) { in nvc0_vp_assign_input_slots()
109 switch (info->in[i].sn) { in nvc0_vp_assign_input_slots()
112 info->in[i].mask = 0x1; in nvc0_vp_assign_input_slots()
113 info->in[i].slot[0] = in nvc0_vp_assign_input_slots()
114 nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4; in nvc0_vp_assign_input_slots()
120 info->in[i].slot[c] = (0x80 + n * 0x10 + c * 0x4) / 4; in nvc0_vp_assign_input_slots()
128 nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info) in nvc0_sp_assign_input_slots() argument
130 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10); in nvc0_sp_assign_input_slots()
134 for (i = 0; i < info->numInputs; ++i) { in nvc0_sp_assign_input_slots()
135 offset = nvc0_shader_input_address(info->in[i].sn, in nvc0_sp_assign_input_slots()
136 info->in[i].si, ubase); in nvc0_sp_assign_input_slots()
137 if (info->in[i].patch && offset >= 0x20) in nvc0_sp_assign_input_slots()
138 offset = 0x20 + info->in[i].si * 0x10; in nvc0_sp_assign_input_slots()
140 if (info->in[i].sn == NV50_SEMANTIC_TESSCOORD) in nvc0_sp_assign_input_slots()
141 info->in[i].mask &= 3; in nvc0_sp_assign_input_slots()
144 info->in[i].slot[c] = (offset + c * 0x4) / 4; in nvc0_sp_assign_input_slots()
146 nvc0_mesa_varying_hack(&info->in[i]); in nvc0_sp_assign_input_slots()
153 nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info) in nvc0_fp_assign_output_slots() argument
155 unsigned count = info->prop.fp.numColourResults * 4; in nvc0_fp_assign_output_slots()
158 for (i = 0; i < info->numOutputs; ++i) in nvc0_fp_assign_output_slots()
159 if (info->out[i].sn == TGSI_SEMANTIC_COLOR) in nvc0_fp_assign_output_slots()
161 info->out[i].slot[c] = info->out[i].si * 4 + c; in nvc0_fp_assign_output_slots()
163 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS) in nvc0_fp_assign_output_slots()
164 info->out[info->io.sampleMask].slot[0] = count++; in nvc0_fp_assign_output_slots()
166 if (info->target >= 0xe0) in nvc0_fp_assign_output_slots()
169 if (info->io.fragDepth < PIPE_MAX_SHADER_OUTPUTS) in nvc0_fp_assign_output_slots()
170 info->out[info->io.fragDepth].slot[2] = count; in nvc0_fp_assign_output_slots()
176 nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info) in nvc0_sp_assign_output_slots() argument
178 unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10); in nvc0_sp_assign_output_slots()
182 for (i = 0; i < info->numOutputs; ++i) { in nvc0_sp_assign_output_slots()
183 offset = nvc0_shader_output_address(info->out[i].sn, in nvc0_sp_assign_output_slots()
184 info->out[i].si, ubase); in nvc0_sp_assign_output_slots()
185 if (info->out[i].patch && offset >= 0x20) in nvc0_sp_assign_output_slots()
186 offset = 0x20 + info->out[i].si * 0x10; in nvc0_sp_assign_output_slots()
189 info->out[i].slot[c] = (offset + c * 0x4) / 4; in nvc0_sp_assign_output_slots()
191 nvc0_mesa_varying_hack(&info->out[i]); in nvc0_sp_assign_output_slots()
198 nvc0_program_assign_varying_slots(struct nv50_ir_prog_info *info) in nvc0_program_assign_varying_slots() argument
202 if (info->type == PIPE_SHADER_VERTEX) in nvc0_program_assign_varying_slots()
203 ret = nvc0_vp_assign_input_slots(info); in nvc0_program_assign_varying_slots()
205 ret = nvc0_sp_assign_input_slots(info); in nvc0_program_assign_varying_slots()
209 if (info->type == PIPE_SHADER_FRAGMENT) in nvc0_program_assign_varying_slots()
210 ret = nvc0_fp_assign_output_slots(info); in nvc0_program_assign_varying_slots()
212 ret = nvc0_sp_assign_output_slots(info); in nvc0_program_assign_varying_slots()
230 nvc0_vtgp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info) in nvc0_vtgp_gen_header() argument
234 for (i = 0; i < info->numInputs; ++i) { in nvc0_vtgp_gen_header()
235 if (info->in[i].patch) in nvc0_vtgp_gen_header()
238 a = info->in[i].slot[c]; in nvc0_vtgp_gen_header()
239 if (info->in[i].mask & (1 << c)) { in nvc0_vtgp_gen_header()
240 if (info->in[i].sn != NV50_SEMANTIC_TESSCOORD) in nvc0_vtgp_gen_header()
243 nvc0_vtgp_hdr_update_oread(vp, info->in[i].slot[c]); in nvc0_vtgp_gen_header()
248 for (i = 0; i < info->numOutputs; ++i) { in nvc0_vtgp_gen_header()
249 if (info->out[i].patch) in nvc0_vtgp_gen_header()
252 if (!(info->out[i].mask & (1 << c))) in nvc0_vtgp_gen_header()
254 assert(info->out[i].slot[c] >= 0x40 / 4); in nvc0_vtgp_gen_header()
255 a = info->out[i].slot[c] - 0x40 / 4; in nvc0_vtgp_gen_header()
257 if (info->out[i].oread) in nvc0_vtgp_gen_header()
258 nvc0_vtgp_hdr_update_oread(vp, info->out[i].slot[c]); in nvc0_vtgp_gen_header()
262 for (i = 0; i < info->numSysVals; ++i) { in nvc0_vtgp_gen_header()
263 switch (info->sv[i].sn) { in nvc0_vtgp_gen_header()
278 vp->vp.clip_enable = info->io.clipDistanceMask; in nvc0_vtgp_gen_header()
280 if (info->io.cullDistanceMask & (1 << i)) in nvc0_vtgp_gen_header()
283 if (info->io.genUserClip < 0) in nvc0_vtgp_gen_header()
290 nvc0_vp_gen_header(struct nvc0_program *vp, struct nv50_ir_prog_info *info) in nvc0_vp_gen_header() argument
295 vp->hdr[18] = info->io.clipDistanceMask; in nvc0_vp_gen_header()
297 return nvc0_vtgp_gen_header(vp, info); in nvc0_vp_gen_header()
302 nvc0_tp_get_tess_mode(struct nvc0_program *tp, struct nv50_ir_prog_info *info) in nvc0_tp_get_tess_mode() argument
304 if (info->prop.tp.outputPrim == PIPE_PRIM_MAX) { in nvc0_tp_get_tess_mode()
308 switch (info->prop.tp.domain) { in nvc0_tp_get_tess_mode()
314 if (info->prop.tp.winding > 0) in nvc0_tp_get_tess_mode()
324 if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS) in nvc0_tp_get_tess_mode()
327 switch (info->prop.tp.partitioning) { in nvc0_tp_get_tess_mode()
347 nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info) in nvc0_tcp_gen_header() argument
351 tcp->tp.input_patch_size = info->prop.tp.inputPatchSize; in nvc0_tcp_gen_header()
353 if (info->numPatchConstants) in nvc0_tcp_gen_header()
354 opcs = 8 + info->numPatchConstants * 4; in nvc0_tcp_gen_header()
359 tcp->hdr[2] = info->prop.tp.outputPatchSize << 24; in nvc0_tcp_gen_header()
363 nvc0_vtgp_gen_header(tcp, info); in nvc0_tcp_gen_header()
365 nvc0_tp_get_tess_mode(tcp, info); in nvc0_tcp_gen_header()
373 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info) in nvc0_tep_gen_header() argument
380 nvc0_vtgp_gen_header(tep, info); in nvc0_tep_gen_header()
382 nvc0_tp_get_tess_mode(tep, info); in nvc0_tep_gen_header()
391 nvc0_gp_gen_header(struct nvc0_program *gp, struct nv50_ir_prog_info *info) in nvc0_gp_gen_header() argument
395 gp->hdr[2] = MIN2(info->prop.gp.instanceCount, 32) << 24; in nvc0_gp_gen_header()
397 switch (info->prop.gp.outputPrim) { in nvc0_gp_gen_header()
415 gp->hdr[4] = info->prop.gp.maxVertices & 0x1ff; in nvc0_gp_gen_header()
417 return nvc0_vtgp_gen_header(gp, info); in nvc0_gp_gen_header()
436 nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info) in nvc0_fp_gen_header() argument
444 if (info->prop.fp.usesDiscard) in nvc0_fp_gen_header()
446 if (info->prop.fp.numColourResults > 1) in nvc0_fp_gen_header()
448 if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS) in nvc0_fp_gen_header()
450 if (info->prop.fp.writesDepth) { in nvc0_fp_gen_header()
455 for (i = 0; i < info->numInputs; ++i) { in nvc0_fp_gen_header()
456 m = nvc0_hdr_interp_mode(&info->in[i]); in nvc0_fp_gen_header()
458 if (!(info->in[i].mask & (1 << c))) in nvc0_fp_gen_header()
460 a = info->in[i].slot[c]; in nvc0_fp_gen_header()
461 if (info->in[i].slot[0] >= (0x060 / 4) && in nvc0_fp_gen_header()
462 info->in[i].slot[0] <= (0x07c / 4)) { in nvc0_fp_gen_header()
465 if (info->in[i].slot[0] >= (0x2c0 / 4) && in nvc0_fp_gen_header()
466 info->in[i].slot[0] <= (0x2fc / 4)) { in nvc0_fp_gen_header()
469 if (info->in[i].slot[c] < (0x040 / 4) || in nvc0_fp_gen_header()
470 info->in[i].slot[c] > (0x380 / 4)) in nvc0_fp_gen_header()
473 if (info->in[i].slot[0] >= (0x300 / 4)) in nvc0_fp_gen_header()
480 for (i = 0; i < info->numOutputs; ++i) { in nvc0_fp_gen_header()
481 if (info->out[i].sn == TGSI_SEMANTIC_COLOR) in nvc0_fp_gen_header()
482 fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0]; in nvc0_fp_gen_header()
485 fp->fp.early_z = info->prop.fp.earlyFragTests; in nvc0_fp_gen_header()
491 nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info, in nvc0_program_create_tfb_state() argument
513 info->out[pso->output[i].register_index].slot[s + c]; in nvc0_program_create_tfb_state()
547 struct nv50_ir_prog_info *info; in nvc0_program_translate() local
550 info = CALLOC_STRUCT(nv50_ir_prog_info); in nvc0_program_translate()
551 if (!info) in nvc0_program_translate()
554 info->type = prog->type; in nvc0_program_translate()
555 info->target = chipset; in nvc0_program_translate()
556 info->bin.sourceRep = NV50_PROGRAM_IR_TGSI; in nvc0_program_translate()
557 info->bin.source = (void *)prog->pipe.tokens; in nvc0_program_translate()
559 info->io.genUserClip = prog->vp.num_ucps; in nvc0_program_translate()
560 info->io.ucpBase = 256; in nvc0_program_translate()
561 info->io.ucpBinding = 15; in nvc0_program_translate()
563 info->assignSlots = nvc0_program_assign_varying_slots; in nvc0_program_translate()
566 info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3); in nvc0_program_translate()
567 info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0); in nvc0_program_translate()
569 info->optLevel = 3; in nvc0_program_translate()
572 ret = nv50_ir_generate_code(info); in nvc0_program_translate()
577 if (info->bin.syms) /* we don't need them yet */ in nvc0_program_translate()
578 FREE(info->bin.syms); in nvc0_program_translate()
580 prog->code = info->bin.code; in nvc0_program_translate()
581 prog->code_size = info->bin.codeSize; in nvc0_program_translate()
582 prog->immd_data = info->immd.buf; in nvc0_program_translate()
583 prog->immd_size = info->immd.bufSize; in nvc0_program_translate()
584 prog->relocs = info->bin.relocData; in nvc0_program_translate()
585 prog->max_gpr = MAX2(4, (info->bin.maxGPR + 1)); in nvc0_program_translate()
587 prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS; in nvc0_program_translate()
589 if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS) in nvc0_program_translate()
590 info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */ in nvc0_program_translate()
591 prog->vp.edgeflag = info->io.edgeFlagIn; in nvc0_program_translate()
595 ret = nvc0_vp_gen_header(prog, info); in nvc0_program_translate()
599 ret = nvc0_tcp_gen_header(prog, info); in nvc0_program_translate()
604 ret = nvc0_tep_gen_header(prog, info); in nvc0_program_translate()
608 ret = nvc0_gp_gen_header(prog, info); in nvc0_program_translate()
611 ret = nvc0_fp_gen_header(prog, info); in nvc0_program_translate()
621 if (info->bin.tlsSpace) { in nvc0_program_translate()
622 assert(info->bin.tlsSpace < (1 << 24)); in nvc0_program_translate()
624 prog->hdr[1] |= info->bin.tlsSpace; /* l[] size */ in nvc0_program_translate()
631 if ((info->maxCFDepth * 2) > 16) { in nvc0_program_translate()
632 prog->hdr[2] |= (((info->maxCFDepth * 2) + 47) / 48) * 0x200; in nvc0_program_translate()
636 if (info->io.globalAccess) in nvc0_program_translate()
640 prog->tfb = nvc0_program_create_tfb_state(info, in nvc0_program_translate()
644 FREE(info); in nvc0_program_translate()