Lines Matching refs:SDValue

27   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
28   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
35   SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
38   bool isHWTrueValue(SDValue Op) const;
39   bool isHWFalseValue(SDValue Op) const;
44   virtual SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
48                              SmallVectorImpl<SDValue> &InVals) const;
50   virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
53                               const SmallVectorImpl<SDValue> &OutVals,
56   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
57   SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
58   SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
67   virtual void computeMaskedBitsForTargetNode(const SDValue Op,
84   SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
85   SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
86   SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
87   SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
88   SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
89   SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
90   SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
91   SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
92   SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
93   SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
94   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
96   SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
97   SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;