110     setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom);  in InitAMDILLowering()
111     setOperationAction(ISD::SUBE, VT, Expand);  in InitAMDILLowering()
112     setOperationAction(ISD::SUBC, VT, Expand);  in InitAMDILLowering()
113     setOperationAction(ISD::ADDE, VT, Expand);  in InitAMDILLowering()
114     setOperationAction(ISD::ADDC, VT, Expand);  in InitAMDILLowering()
115     setOperationAction(ISD::BRCOND, VT, Custom);  in InitAMDILLowering()
116     setOperationAction(ISD::BR_JT, VT, Expand);  in InitAMDILLowering()
117     setOperationAction(ISD::BRIND, VT, Expand);  in InitAMDILLowering()
119     setOperationAction(ISD::SREM, VT, Expand);  in InitAMDILLowering()
120     setOperationAction(ISD::SMUL_LOHI, VT, Expand);  in InitAMDILLowering()
121     setOperationAction(ISD::UMUL_LOHI, VT, Expand);  in InitAMDILLowering()
123       setOperationAction(ISD::SDIV, VT, Custom);  in InitAMDILLowering()
130     setOperationAction(ISD::FP_ROUND_INREG, VT, Expand);  in InitAMDILLowering()
131     setOperationAction(ISD::SETOLT, VT, Expand);  in InitAMDILLowering()
132     setOperationAction(ISD::SETOGE, VT, Expand);  in InitAMDILLowering()
133     setOperationAction(ISD::SETOGT, VT, Expand);  in InitAMDILLowering()
134     setOperationAction(ISD::SETOLE, VT, Expand);  in InitAMDILLowering()
135     setOperationAction(ISD::SETULT, VT, Expand);  in InitAMDILLowering()
136     setOperationAction(ISD::SETUGE, VT, Expand);  in InitAMDILLowering()
137     setOperationAction(ISD::SETUGT, VT, Expand);  in InitAMDILLowering()
138     setOperationAction(ISD::SETULE, VT, Expand);  in InitAMDILLowering()
145     setOperationAction(ISD::SDIVREM, VT, Expand);  in InitAMDILLowering()
148     setOperationAction(ISD::SMUL_LOHI, VT, Expand);  in InitAMDILLowering()
149     setOperationAction(ISD::UMUL_LOHI, VT, Expand);  in InitAMDILLowering()
152     setOperationAction(ISD::ROTR, VT, Expand);  in InitAMDILLowering()
153     setOperationAction(ISD::BSWAP, VT, Expand);  in InitAMDILLowering()
156     setOperationAction(ISD::CTPOP, VT, Expand);  in InitAMDILLowering()
157     setOperationAction(ISD::CTTZ, VT, Expand);  in InitAMDILLowering()
158     setOperationAction(ISD::CTLZ, VT, Expand);  in InitAMDILLowering()
165     setOperationAction(ISD::BUILD_VECTOR, VT, Custom);  in InitAMDILLowering()
166     setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);  in InitAMDILLowering()
167     setOperationAction(ISD::SDIVREM, VT, Expand);  in InitAMDILLowering()
168     setOperationAction(ISD::SMUL_LOHI, VT, Expand);  in InitAMDILLowering()
170     setOperationAction(ISD::SELECT_CC, VT, Expand);  in InitAMDILLowering()
174     setOperationAction(ISD::MULHU, MVT::i64, Expand);  in InitAMDILLowering()
175     setOperationAction(ISD::MULHU, MVT::v2i64, Expand);  in InitAMDILLowering()
176     setOperationAction(ISD::MULHS, MVT::i64, Expand);  in InitAMDILLowering()
177     setOperationAction(ISD::MULHS, MVT::v2i64, Expand);  in InitAMDILLowering()
178     setOperationAction(ISD::ADD, MVT::v2i64, Expand);  in InitAMDILLowering()
179     setOperationAction(ISD::SREM, MVT::v2i64, Expand);  in InitAMDILLowering()
180     setOperationAction(ISD::Constant          , MVT::i64  , Legal);  in InitAMDILLowering()
181     setOperationAction(ISD::SDIV, MVT::v2i64, Expand);  in InitAMDILLowering()
182     setOperationAction(ISD::TRUNCATE, MVT::v2i64, Expand);  in InitAMDILLowering()
183     setOperationAction(ISD::SIGN_EXTEND, MVT::v2i64, Expand);  in InitAMDILLowering()
184     setOperationAction(ISD::ZERO_EXTEND, MVT::v2i64, Expand);  in InitAMDILLowering()
185     setOperationAction(ISD::ANY_EXTEND, MVT::v2i64, Expand);  in InitAMDILLowering()
189     setOperationAction(ISD::FADD, MVT::v2f64, Expand);  in InitAMDILLowering()
190     setOperationAction(ISD::FSUB, MVT::v2f64, Expand);  in InitAMDILLowering()
191     setOperationAction(ISD::FMUL, MVT::v2f64, Expand);  in InitAMDILLowering()
192     setOperationAction(ISD::FP_ROUND_INREG, MVT::v2f64, Expand);  in InitAMDILLowering()
193     setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);  in InitAMDILLowering()
194     setOperationAction(ISD::ConstantFP        , MVT::f64  , Legal);  in InitAMDILLowering()
197     setOperationAction(ISD::TRUNCATE, MVT::v2f64, Expand);  in InitAMDILLowering()
198     setOperationAction(ISD::SIGN_EXTEND, MVT::v2f64, Expand);  in InitAMDILLowering()
199     setOperationAction(ISD::ZERO_EXTEND, MVT::v2f64, Expand);  in InitAMDILLowering()
200     setOperationAction(ISD::ANY_EXTEND, MVT::v2f64, Expand);  in InitAMDILLowering()
201     setOperationAction(ISD::FABS, MVT::f64, Expand);  in InitAMDILLowering()
202     setOperationAction(ISD::FABS, MVT::v2f64, Expand);  in InitAMDILLowering()
207   setOperationAction(ISD::UDIV, MVT::v2i8, Expand);  in InitAMDILLowering()
208   setOperationAction(ISD::UDIV, MVT::v4i8, Expand);  in InitAMDILLowering()
209   setOperationAction(ISD::UDIV, MVT::v2i16, Expand);  in InitAMDILLowering()
210   setOperationAction(ISD::UDIV, MVT::v4i16, Expand);  in InitAMDILLowering()
211   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Custom);  in InitAMDILLowering()
212   setOperationAction(ISD::SUBC, MVT::Other, Expand);  in InitAMDILLowering()
213   setOperationAction(ISD::ADDE, MVT::Other, Expand);  in InitAMDILLowering()
214   setOperationAction(ISD::ADDC, MVT::Other, Expand);  in InitAMDILLowering()
215   setOperationAction(ISD::BRCOND, MVT::Other, Custom);  in InitAMDILLowering()
216   setOperationAction(ISD::BR_JT, MVT::Other, Expand);  in InitAMDILLowering()
217   setOperationAction(ISD::BRIND, MVT::Other, Expand);  in InitAMDILLowering()
218   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Expand);  in InitAMDILLowering()
220   setOperationAction(ISD::BUILD_VECTOR, MVT::Other, Custom);  in InitAMDILLowering()
223   setOperationAction(ISD::ConstantFP        , MVT::f32    , Legal);  in InitAMDILLowering()
224   setOperationAction(ISD::Constant          , MVT::i32    , Legal);  in InitAMDILLowering()
289     case ISD::SELECT_CC:  in computeMaskedBitsForTargetNode()
383       if (fourth.getOpcode() != ISD::UNDEF) {  in LowerBUILD_VECTOR()
385             ISD::INSERT_VECTOR_ELT,  in LowerBUILD_VECTOR()
394       if (third.getOpcode() != ISD::UNDEF) {  in LowerBUILD_VECTOR()
396             ISD::INSERT_VECTOR_ELT,  in LowerBUILD_VECTOR()
405       if (second.getOpcode() != ISD::UNDEF) {  in LowerBUILD_VECTOR()
407             ISD::INSERT_VECTOR_ELT,  in LowerBUILD_VECTOR()
434     Data = DAG.getNode(ISD::ZERO_EXTEND, DL, IVT, Data);  in LowerSIGN_EXTEND_INREG()
440   Data = DAG.getNode(ISD::SHL, DL, DVT, Data, Shift);  in LowerSIGN_EXTEND_INREG()
442   Data = DAG.getNode(ISD::SRA, DL, DVT, Data, Shift);  in LowerSIGN_EXTEND_INREG()
509   SDValue jq = DAG.getNode(ISD::XOR, DL, OVT, LHS, RHS);  in LowerSDIV24()
512   jq = DAG.getNode(ISD::SRA, DL, OVT, jq, DAG.getConstant(bitsize - 2, OVT));   in LowerSDIV24()
515   jq = DAG.getNode(ISD::OR, DL, OVT, jq, DAG.getConstant(1, OVT));  in LowerSDIV24()
527   SDValue fa = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ia);  in LowerSDIV24()
530   SDValue fb = DAG.getNode(ISD::SINT_TO_FP, DL, FLTTY, ib);  in LowerSDIV24()
536   fq = DAG.getNode(ISD::FTRUNC, DL, FLTTY, fq);  in LowerSDIV24()
539   SDValue fqneg = DAG.getNode(ISD::FNEG, DL, FLTTY, fq);  in LowerSDIV24()
545   SDValue iq = DAG.getNode(ISD::FP_TO_SINT, DL, INTTY, fq);  in LowerSDIV24()
548   fr = DAG.getNode(ISD::FABS, DL, FLTTY, fr);  in LowerSDIV24()
551   fb = DAG.getNode(ISD::FABS, DL, FLTTY, fb);  in LowerSDIV24()
556     cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);  in LowerSDIV24()
558     cv = DAG.getSetCC(DL, INTTY, fr, fb, ISD::SETOGE);  in LowerSDIV24()
561   jq = DAG.getNode(ISD::SELECT, DL, OVT, cv, jq,   in LowerSDIV24()
565   iq = DAG.getNode(ISD::ADD, DL, OVT, iq, jq);  in LowerSDIV24()
601       ISD::SETLT);  in LowerSDIV32()
608       ISD::SETLT);  in LowerSDIV32()
611   r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);  in LowerSDIV32()
614   r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);  in LowerSDIV32()
617   r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);  in LowerSDIV32()
620   r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);  in LowerSDIV32()
623   r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1);  in LowerSDIV32()
626   r10 = DAG.getNode(ISD::XOR, DL, OVT, r10, r11);  in LowerSDIV32()
629   r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);  in LowerSDIV32()
632   SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);   in LowerSDIV32()
655   LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);  in LowerSREM8()
673   LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);  in LowerSREM16()
707   SDValue r10 = DAG.getSetCC(DL, OVT, r0, DAG.getConstant(0, OVT), ISD::SETLT);  in LowerSREM32()
710   SDValue r11 = DAG.getSetCC(DL, OVT, r1, DAG.getConstant(0, OVT), ISD::SETLT);  in LowerSREM32()
713   r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);  in LowerSREM32()
716   r1 = DAG.getNode(ISD::ADD, DL, OVT, r1, r11);  in LowerSREM32()
719   r0 = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);  in LowerSREM32()
722   r1 = DAG.getNode(ISD::XOR, DL, OVT, r1, r11);  in LowerSREM32()
725   SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);  in LowerSREM32()
731   r0 = DAG.getNode(ISD::SUB, DL, OVT, r0, r20);  in LowerSREM32()
734   r0 = DAG.getNode(ISD::ADD, DL, OVT, r0, r10);  in LowerSREM32()
737   SDValue DST = DAG.getNode(ISD::XOR, DL, OVT, r0, r10);   in LowerSREM32()