Lines Matching refs:addReg
59 .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) in copyPhysReg()
60 .addReg(RI.getSubReg(SrcReg, SubRegIndex)) in copyPhysReg()
62 .addReg(0) // PREDICATE_BIT in copyPhysReg()
63 .addReg(DestReg, RegState::Define | RegState::Implicit); in copyPhysReg()
72 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
74 .addReg(0); // PREDICATE_BIT in copyPhysReg()
82 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); in getMovImmInstr()
83 MachineInstrBuilder(MI).addReg(AMDGPU::ALU_LITERAL_X); in getMovImmInstr()
85 MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT in getMovImmInstr()
271 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB).addReg(0); in InsertBranch()
281 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); in InsertBranch()
291 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); in InsertBranch()
292 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB).addReg(0); in InsertBranch()
463 MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit); in PredicateInstruction()