Lines Matching refs:src0
92 (ins R600_Reg32:$src0, R600_Reg32:$src1,R600_Pred:$p, variable_ops),
93 !strconcat(opName, " $dst, $src0, $src1"),
102 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2,R600_Pred:$p, variable_ops),
103 !strconcat(opName, " $dst, $src0, $src1, $src2"),
113 (ins R600_Reg32:$src0, i32imm:$src1, i32imm:$flags),
114 "PRED $dst, $src0, $src1",
117 let DisableEncoding = "$src0";
149 (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2),
150 !strconcat(opName, "$dst, $src0, $src1, $src2"),
243 [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
249 [(set R600_Reg32:$dst, (int_AMDGPU_mul R600_Reg32:$src0, R600_Reg32:$src1))]
254 [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
259 [(set R600_Reg32:$dst, (AMDGPUfmax R600_Reg32:$src0, R600_Reg32:$src1))]
264 [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
274 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
281 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
288 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
295 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO,
325 (ins R600_Reg32:$src0, i32imm:$flags,
327 "MOV $dst, $src0", [], AnyALU> {
352 (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags, R600_Pred:$p,
354 "KILLGT $dst, $src0, $src1, $flags ($p)",
362 [(set R600_Reg32:$dst, (and R600_Reg32:$src0, R600_Reg32:$src1))]
367 [(set R600_Reg32:$dst, (or R600_Reg32:$src0, R600_Reg32:$src1))]
372 [(set R600_Reg32:$dst, (xor R600_Reg32:$src0, R600_Reg32:$src1))]
382 [(set R600_Reg32:$dst, (add R600_Reg32:$src0, R600_Reg32:$src1))]
387 [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))]
392 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
396 [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
400 [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
405 [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
411 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETEQ))]
417 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGT))]
423 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETGE))]
429 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETNE))]
435 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGT))]
441 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETUGE))]
447 (select R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
456 …[(set R600_Reg128:$dst, (int_AMDGPU_txf R600_Reg128:$src0, imm:$src1, imm:$src2, imm:$src3, imm:$s…
458 let AsmString = "TEX_LD $dst, $src0, $src1, $src2, $src3, $src4, $src5";
459 let InOperandList = (ins R600_Reg128:$src0, i32imm:$src1, i32imm:$src2, i32imm:$src3, i32imm:$src4,…
464 [(set R600_Reg128:$dst, (int_AMDGPU_txq R600_Reg128:$src0, imm:$src1, imm:$src2))]
469 [(set R600_Reg128:$dst, (int_AMDGPU_ddx R600_Reg128:$src0, imm:$src1, imm:$src2))]
474 [(set R600_Reg128:$dst, (int_AMDGPU_ddy R600_Reg128:$src0, imm:$src1, imm:$src2))]
489 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, imm:$src2))]
494 [(set R600_Reg128:$dst, (int_AMDGPU_tex R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
499 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, imm:$src2))]
504 [(set R600_Reg128:$dst, (int_AMDGPU_txl R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
509 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, imm:$src2))]
514 [(set R600_Reg128:$dst, (int_AMDGPU_txb R600_Reg128:$src0, imm:$src1, TEX_SHADOW:$src2))]
539 (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
545 …(select (i32 (fp_to_sint (fneg R600_Reg32:$src0))), (f32 R600_Reg32:$src2), (f32 R600_Reg32:$src1)…
555 [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
560 (ins R600_Reg128:$src0, R600_Reg128:$src1, i32imm:$flags),
561 "DOT4 $dst $src0, $src1",
568 (int_AMDGPU_dp4 R600_Reg128:$src0, R600_Reg128:$src1),
569 (dot4 R600_Reg128:$src0, R600_Reg128:$src1, 0)
586 (ins R600_Reg32:$src0, R600_Reg32:$src1, i32imm:$flags),
587 "CUBE $dst, $src0, $src1",
630 inst, "LSHL $dst, $src0, $src1",
631 [(set R600_Reg32:$dst, (shl R600_Reg32:$src0, R600_Reg32:$src1))]
635 inst, "LSHR $dst, $src0, $src1",
636 [(set R600_Reg32:$dst, (srl R600_Reg32:$src0, R600_Reg32:$src1))]
640 inst, "ASHR $dst, $src0, $src1",
641 [(set R600_Reg32:$dst, (sra R600_Reg32:$src0, R600_Reg32:$src1))]
645 inst, "MULHI_INT $dst, $src0, $src1",
646 [(set R600_Reg32:$dst, (mulhs R600_Reg32:$src0, R600_Reg32:$src1))]
650 inst, "MULHI $dst, $src0, $src1",
651 [(set R600_Reg32:$dst, (mulhu R600_Reg32:$src0, R600_Reg32:$src1))]
655 inst, "MULLO_INT $dst, $src0, $src1",
656 [(set R600_Reg32:$dst, (mul R600_Reg32:$src0, R600_Reg32:$src1))]
660 inst, "MULLO_UINT $dst, $src0, $src1",
704 (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
705 (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
818 [(set R600_Reg32:$dst, (int_AMDIL_bit_extract_u32 R600_Reg32:$src0,
825 [(set R600_Reg32:$dst, (AMDGPUbitalign R600_Reg32:$src0, R600_Reg32:$src1,
1084 (AMDGPUurecip R600_Reg32:$src0),
1085 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg R600_Reg32:$src0)),
1095 (ins R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
1096 "MULLIT $dst, $src0, $src1",
1097 … [(set R600_Reg128:$dst, (int_AMDGPU_mullit R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
1111 (ins i32imm:$src0),
1112 "R600_LOAD_CONST $dst, $src0",
1113 [(set R600_Reg32:$dst, (int_AMDGPU_load_const imm:$src0))]
1125 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1126 "TXD $dst, $src0, $src1, $src2, $src3, $src4",
1127 …[(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i…
1132 (ins R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i32imm:$src3, i32imm:$src4),
1133 "TXD_SHADOW $dst, $src0, $src1, $src2, $src3, $src4",
1134 …[(set R600_Reg128:$dst, (int_AMDGPU_txd R600_Reg128:$src0, R600_Reg128:$src1, R600_Reg128:$src2, i…
1175 (int_AMDGPU_kill R600_Reg32:$src0),
1176 (MASK_WRITE (KILLGT (f32 ZERO), (f32 R600_Reg32:$src0), 0))
1181 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LT),
1182 (SGT R600_Reg32:$src1, R600_Reg32:$src0)
1187 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, COND_LE),
1188 (SGE R600_Reg32:$src1, R600_Reg32:$src0)
1193 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLT),
1194 (SETGT_INT R600_Reg32:$src1, R600_Reg32:$src0)
1199 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETLE),
1200 (SETGE_INT R600_Reg32:$src1, R600_Reg32:$src0)
1205 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULT),
1206 (SETGT_UINT R600_Reg32:$src1, R600_Reg32:$src0)
1211 (selectcc (i32 R600_Reg32:$src0), R600_Reg32:$src1, -1, 0, SETULE),
1212 (SETGE_UINT R600_Reg32:$src0, R600_Reg32:$src1)
1225 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETO),
1226 (SETE R600_Reg32:$src0, R600_Reg32:$src1)
1231 (selectcc (f32 R600_Reg32:$src0), R600_Reg32:$src1, FP_ONE, FP_ZERO, SETUO),
1232 (SNE R600_Reg32:$src0, R600_Reg32:$src1)