Lines Matching refs:bits
34 field bits<4> EncodingType = 0;
35 field bits<1> NeedWait = 0;
45 field bits<32> Inst;
51 field bits<64> Inst;
94 // i64Literal is really a i32 literal with the top 32-bits all set to zero.
119 bits<4> EN;
120 bits<6> TGT;
121 bits<1> COMPR;
122 bits<1> DONE;
123 bits<1> VM;
124 bits<8> VSRC0;
125 bits<8> VSRC1;
126 bits<8> VSRC2;
127 bits<8> VSRC3;
145 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
148 bits<8> VDATA;
149 bits<4> DMASK;
150 bits<1> UNORM;
151 bits<1> GLC;
152 bits<1> DA;
153 bits<1> R128;
154 bits<1> TFE;
155 bits<1> LWE;
156 bits<1> SLC;
157 bits<8> VADDR;
158 bits<5> SRSRC;
159 bits<5> SSAMP;
182 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
185 bits<8> VDATA;
186 bits<12> OFFSET;
187 bits<1> OFFEN;
188 bits<1> IDXEN;
189 bits<1> GLC;
190 bits<1> ADDR64;
191 bits<4> DFMT;
192 bits<3> NFMT;
193 bits<8> VADDR;
194 bits<5> SRSRC;
195 bits<1> SLC;
196 bits<1> TFE;
197 bits<8> SOFFSET;
221 class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
224 bits<8> VDATA;
225 bits<12> OFFSET;
226 bits<1> OFFEN;
227 bits<1> IDXEN;
228 bits<1> GLC;
229 bits<1> ADDR64;
230 bits<1> LDS;
231 bits<8> VADDR;
232 bits<5> SRSRC;
233 bits<1> SLC;
234 bits<1> TFE;
235 bits<8> SOFFSET;
258 class SMRD <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
261 bits<7> SDST;
262 bits<15> PTR;
263 bits<8> OFFSET = PTR{7-0};
264 bits<1> IMM = PTR{8};
265 bits<6> SBASE = PTR{14-9};
279 class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
282 bits<7> SDST;
283 bits<8> SSRC0;
292 class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
295 bits<7> SDST;
296 bits<8> SSRC0;
297 bits<8> SSRC1;
307 class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
310 bits<8> SSRC0;
311 bits<8> SSRC1;
322 class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
325 bits <7> SDST;
326 bits <16> SIMM16;
335 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
341 bits <16> SIMM16;
350 class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
353 bits<8> VDST;
354 bits<8> VSRC;
355 bits<2> ATTRCHAN;
356 bits<6> ATTR;
369 class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
372 bits<8> VDST;
373 bits<9> SRC0;
384 class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
387 bits<8> VDST;
388 bits<9> SRC0;
389 bits<8> VSRC1;
401 class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
404 bits<8> VDST;
405 bits<9> SRC0;
406 bits<9> SRC1;
407 bits<9> SRC2;
408 bits<3> ABS;
409 bits<1> CLAMP;
410 bits<2> OMOD;
411 bits<3> NEG;
428 class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
431 bits<9> SRC0;
432 bits<8> VSRC1;
444 class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
454 class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
465 class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
476 class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
487 multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass,
506 multiclass SMRD_32 <bits<5> op, string asm, RegisterClass dstClass> {