Lines Matching refs:rd
350 Register rd; in GetRdReg() local
351 rd.code_ = (instr & kRdFieldMask) >> kRdShift; in GetRdReg()
352 return rd; in GetRdReg()
564 uint32_t rd = GetRd(instr); in IsNop() local
574 rd == static_cast<uint32_t>(ToNumber(zero_reg)) && in IsNop()
853 Register rd, in GenInstrRegister() argument
856 DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); in GenInstrRegister()
858 | (rd.code() << kRdShift) | (sa << kSaShift) | func; in GenInstrRegister()
1411 void Assembler::jalr(Register rs, Register rd) { in jalr() argument
1414 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); in jalr()
1449 void Assembler::addu(Register rd, Register rs, Register rt) { in addu() argument
1450 GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU); in addu()
1454 void Assembler::addiu(Register rd, Register rs, int32_t j) { in addiu() argument
1455 GenInstrImmediate(ADDIU, rs, rd, j); in addiu()
1459 void Assembler::subu(Register rd, Register rs, Register rt) { in subu() argument
1460 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU); in subu()
1464 void Assembler::mul(Register rd, Register rs, Register rt) { in mul() argument
1466 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH); in mul()
1468 GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL); in mul()
1473 void Assembler::muh(Register rd, Register rs, Register rt) { in muh() argument
1475 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH); in muh()
1479 void Assembler::mulu(Register rd, Register rs, Register rt) { in mulu() argument
1481 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U); in mulu()
1485 void Assembler::muhu(Register rd, Register rs, Register rt) { in muhu() argument
1487 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U); in muhu()
1491 void Assembler::dmul(Register rd, Register rs, Register rt) { in dmul() argument
1493 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH); in dmul()
1497 void Assembler::dmuh(Register rd, Register rs, Register rt) { in dmuh() argument
1499 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH); in dmuh()
1503 void Assembler::dmulu(Register rd, Register rs, Register rt) { in dmulu() argument
1505 GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, D_MUL_MUH_U); in dmulu()
1509 void Assembler::dmuhu(Register rd, Register rs, Register rt) { in dmuhu() argument
1511 GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, D_MUL_MUH_U); in dmuhu()
1527 void Assembler::daddiu(Register rd, Register rs, int32_t j) { in daddiu() argument
1528 GenInstrImmediate(DADDIU, rs, rd, j); in daddiu()
1537 void Assembler::div(Register rd, Register rs, Register rt) { in div() argument
1539 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); in div()
1543 void Assembler::mod(Register rd, Register rs, Register rt) { in mod() argument
1545 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD); in mod()
1554 void Assembler::divu(Register rd, Register rs, Register rt) { in divu() argument
1556 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); in divu()
1560 void Assembler::modu(Register rd, Register rs, Register rt) { in modu() argument
1562 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U); in modu()
1566 void Assembler::daddu(Register rd, Register rs, Register rt) { in daddu() argument
1567 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DADDU); in daddu()
1571 void Assembler::dsubu(Register rd, Register rs, Register rt) { in dsubu() argument
1572 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSUBU); in dsubu()
1591 void Assembler::ddiv(Register rd, Register rs, Register rt) { in ddiv() argument
1593 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD); in ddiv()
1597 void Assembler::dmod(Register rd, Register rs, Register rt) { in dmod() argument
1599 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD); in dmod()
1608 void Assembler::ddivu(Register rd, Register rs, Register rt) { in ddivu() argument
1610 GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, D_DIV_MOD_U); in ddivu()
1614 void Assembler::dmodu(Register rd, Register rs, Register rt) { in dmodu() argument
1616 GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, D_DIV_MOD_U); in dmodu()
1622 void Assembler::and_(Register rd, Register rs, Register rt) { in and_() argument
1623 GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND); in and_()
1633 void Assembler::or_(Register rd, Register rs, Register rt) { in or_() argument
1634 GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR); in or_()
1644 void Assembler::xor_(Register rd, Register rs, Register rt) { in xor_() argument
1645 GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR); in xor_()
1655 void Assembler::nor(Register rd, Register rs, Register rt) { in nor() argument
1656 GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR); in nor()
1661 void Assembler::sll(Register rd, in sll() argument
1669 DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg))); in sll()
1670 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL); in sll()
1674 void Assembler::sllv(Register rd, Register rt, Register rs) { in sllv() argument
1675 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV); in sllv()
1679 void Assembler::srl(Register rd, Register rt, uint16_t sa) { in srl() argument
1680 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL); in srl()
1684 void Assembler::srlv(Register rd, Register rt, Register rs) { in srlv() argument
1685 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV); in srlv()
1689 void Assembler::sra(Register rd, Register rt, uint16_t sa) { in sra() argument
1690 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRA); in sra()
1694 void Assembler::srav(Register rd, Register rt, Register rs) { in srav() argument
1695 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV); in srav()
1699 void Assembler::rotr(Register rd, Register rt, uint16_t sa) { in rotr() argument
1701 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa)); in rotr()
1704 | (rd.code() << kRdShift) | (sa << kSaShift) | SRL; in rotr()
1709 void Assembler::rotrv(Register rd, Register rt, Register rs) { in rotrv() argument
1711 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() ); in rotrv()
1714 | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV; in rotrv()
1719 void Assembler::dsll(Register rd, Register rt, uint16_t sa) { in dsll() argument
1720 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSLL); in dsll()
1724 void Assembler::dsllv(Register rd, Register rt, Register rs) { in dsllv() argument
1725 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSLLV); in dsllv()
1729 void Assembler::dsrl(Register rd, Register rt, uint16_t sa) { in dsrl() argument
1730 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRL); in dsrl()
1734 void Assembler::dsrlv(Register rd, Register rt, Register rs) { in dsrlv() argument
1735 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRLV); in dsrlv()
1739 void Assembler::drotr(Register rd, Register rt, uint16_t sa) { in drotr() argument
1740 DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa)); in drotr()
1742 | (rd.code() << kRdShift) | (sa << kSaShift) | DSRL; in drotr()
1747 void Assembler::drotrv(Register rd, Register rt, Register rs) { in drotrv() argument
1748 DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() ); in drotrv()
1750 | (rd.code() << kRdShift) | (1 << kSaShift) | DSRLV; in drotrv()
1755 void Assembler::dsra(Register rd, Register rt, uint16_t sa) { in dsra() argument
1756 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRA); in dsra()
1760 void Assembler::dsrav(Register rd, Register rt, Register rs) { in dsrav() argument
1761 GenInstrRegister(SPECIAL, rs, rt, rd, 0, DSRAV); in dsrav()
1765 void Assembler::dsll32(Register rd, Register rt, uint16_t sa) { in dsll32() argument
1766 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSLL32); in dsll32()
1770 void Assembler::dsrl32(Register rd, Register rt, uint16_t sa) { in dsrl32() argument
1771 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRL32); in dsrl32()
1775 void Assembler::dsra32(Register rd, Register rt, uint16_t sa) { in dsra32() argument
1776 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, DSRA32); in dsra32()
1793 void Assembler::lb(Register rd, const MemOperand& rs) { in lb() argument
1795 GenInstrImmediate(LB, rs.rm(), rd, rs.offset_); in lb()
1798 GenInstrImmediate(LB, at, rd, 0); // Equiv to lb(rd, MemOperand(at, 0)); in lb()
1803 void Assembler::lbu(Register rd, const MemOperand& rs) { in lbu() argument
1805 GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_); in lbu()
1808 GenInstrImmediate(LBU, at, rd, 0); // Equiv to lbu(rd, MemOperand(at, 0)); in lbu()
1813 void Assembler::lh(Register rd, const MemOperand& rs) { in lh() argument
1815 GenInstrImmediate(LH, rs.rm(), rd, rs.offset_); in lh()
1818 GenInstrImmediate(LH, at, rd, 0); // Equiv to lh(rd, MemOperand(at, 0)); in lh()
1823 void Assembler::lhu(Register rd, const MemOperand& rs) { in lhu() argument
1825 GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_); in lhu()
1828 GenInstrImmediate(LHU, at, rd, 0); // Equiv to lhu(rd, MemOperand(at, 0)); in lhu()
1833 void Assembler::lw(Register rd, const MemOperand& rs) { in lw() argument
1835 GenInstrImmediate(LW, rs.rm(), rd, rs.offset_); in lw()
1838 GenInstrImmediate(LW, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0)); in lw()
1843 void Assembler::lwu(Register rd, const MemOperand& rs) { in lwu() argument
1845 GenInstrImmediate(LWU, rs.rm(), rd, rs.offset_); in lwu()
1848 GenInstrImmediate(LWU, at, rd, 0); // Equiv to lwu(rd, MemOperand(at, 0)); in lwu()
1853 void Assembler::lwl(Register rd, const MemOperand& rs) { in lwl() argument
1854 GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); in lwl()
1858 void Assembler::lwr(Register rd, const MemOperand& rs) { in lwr() argument
1859 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); in lwr()
1863 void Assembler::sb(Register rd, const MemOperand& rs) { in sb() argument
1865 GenInstrImmediate(SB, rs.rm(), rd, rs.offset_); in sb()
1868 GenInstrImmediate(SB, at, rd, 0); // Equiv to sb(rd, MemOperand(at, 0)); in sb()
1873 void Assembler::sh(Register rd, const MemOperand& rs) { in sh() argument
1875 GenInstrImmediate(SH, rs.rm(), rd, rs.offset_); in sh()
1878 GenInstrImmediate(SH, at, rd, 0); // Equiv to sh(rd, MemOperand(at, 0)); in sh()
1883 void Assembler::sw(Register rd, const MemOperand& rs) { in sw() argument
1885 GenInstrImmediate(SW, rs.rm(), rd, rs.offset_); in sw()
1888 GenInstrImmediate(SW, at, rd, 0); // Equiv to sw(rd, MemOperand(at, 0)); in sw()
1893 void Assembler::swl(Register rd, const MemOperand& rs) { in swl() argument
1894 GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); in swl()
1898 void Assembler::swr(Register rd, const MemOperand& rs) { in swr() argument
1899 GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); in swr()
1903 void Assembler::lui(Register rd, int32_t j) { in lui() argument
1905 GenInstrImmediate(LUI, zero_reg, rd, j); in lui()
1935 void Assembler::ldl(Register rd, const MemOperand& rs) { in ldl() argument
1936 GenInstrImmediate(LDL, rs.rm(), rd, rs.offset_); in ldl()
1940 void Assembler::ldr(Register rd, const MemOperand& rs) { in ldr() argument
1941 GenInstrImmediate(LDR, rs.rm(), rd, rs.offset_); in ldr()
1945 void Assembler::sdl(Register rd, const MemOperand& rs) { in sdl() argument
1946 GenInstrImmediate(SDL, rs.rm(), rd, rs.offset_); in sdl()
1950 void Assembler::sdr(Register rd, const MemOperand& rs) { in sdr() argument
1951 GenInstrImmediate(SDR, rs.rm(), rd, rs.offset_); in sdr()
1955 void Assembler::ld(Register rd, const MemOperand& rs) { in ld() argument
1957 GenInstrImmediate(LD, rs.rm(), rd, rs.offset_); in ld()
1960 GenInstrImmediate(LD, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0)); in ld()
1965 void Assembler::sd(Register rd, const MemOperand& rs) { in sd() argument
1967 GenInstrImmediate(SD, rs.rm(), rd, rs.offset_); in sd()
1970 GenInstrImmediate(SD, at, rd, 0); // Equiv to sw(rd, MemOperand(at, 0)); in sd()
2060 void Assembler::mfhi(Register rd) { in mfhi() argument
2061 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI); in mfhi()
2065 void Assembler::mflo(Register rd) { in mflo() argument
2066 GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO); in mflo()
2071 void Assembler::slt(Register rd, Register rs, Register rt) { in slt() argument
2072 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT); in slt()
2076 void Assembler::sltu(Register rd, Register rs, Register rt) { in sltu() argument
2077 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU); in sltu()
2092 void Assembler::movz(Register rd, Register rs, Register rt) { in movz() argument
2093 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ); in movz()
2097 void Assembler::movn(Register rd, Register rs, Register rt) { in movn() argument
2098 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN); in movn()
2102 void Assembler::movt(Register rd, Register rs, uint16_t cc) { in movt() argument
2105 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); in movt()
2109 void Assembler::movf(Register rd, Register rs, uint16_t cc) { in movf() argument
2112 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); in movf()
2129 void Assembler::seleqz(Register rs, Register rt, Register rd) { in seleqz() argument
2131 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELEQZ_S); in seleqz()
2149 void Assembler::selnez(Register rs, Register rt, Register rd) { in selnez() argument
2151 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SELNEZ_S); in selnez()
2169 void Assembler::clz(Register rd, Register rs) { in clz() argument
2172 GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ); in clz()
2174 GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, CLZ_R6); in clz()