Lines Matching refs:CVT
10434 # define CVT(_t) binop( Iop_F64toF32, mkexpr(rmode), mkexpr(_t) ) in dis_CVTPD2PS_128() macro
10437 putXMMRegLane32F( rG, 1, CVT(t1) ); in dis_CVTPD2PS_128()
10438 putXMMRegLane32F( rG, 0, CVT(t0) ); in dis_CVTPD2PS_128()
10439 # undef CVT in dis_CVTPD2PS_128()
10479 # define CVT(_t) \ in dis_CVTxPS2DQ_128() macro
10485 putXMMRegLane32( rG, 3, CVT(t3) ); in dis_CVTxPS2DQ_128()
10486 putXMMRegLane32( rG, 2, CVT(t2) ); in dis_CVTxPS2DQ_128()
10487 putXMMRegLane32( rG, 1, CVT(t1) ); in dis_CVTxPS2DQ_128()
10488 putXMMRegLane32( rG, 0, CVT(t0) ); in dis_CVTxPS2DQ_128()
10489 # undef CVT in dis_CVTxPS2DQ_128()
10529 # define CVT(_t) \ in dis_CVTxPS2DQ_256() macro
10535 putYMMRegLane32( rG, 7, CVT(t7) ); in dis_CVTxPS2DQ_256()
10536 putYMMRegLane32( rG, 6, CVT(t6) ); in dis_CVTxPS2DQ_256()
10537 putYMMRegLane32( rG, 5, CVT(t5) ); in dis_CVTxPS2DQ_256()
10538 putYMMRegLane32( rG, 4, CVT(t4) ); in dis_CVTxPS2DQ_256()
10539 putYMMRegLane32( rG, 3, CVT(t3) ); in dis_CVTxPS2DQ_256()
10540 putYMMRegLane32( rG, 2, CVT(t2) ); in dis_CVTxPS2DQ_256()
10541 putYMMRegLane32( rG, 1, CVT(t1) ); in dis_CVTxPS2DQ_256()
10542 putYMMRegLane32( rG, 0, CVT(t0) ); in dis_CVTxPS2DQ_256()
10543 # undef CVT in dis_CVTxPS2DQ_256()
10588 # define CVT(_t) binop( Iop_F64toI32S, \ in dis_CVTxPD2DQ_128() macro
10594 putXMMRegLane32( rG, 1, CVT(t1) ); in dis_CVTxPD2DQ_128()
10595 putXMMRegLane32( rG, 0, CVT(t0) ); in dis_CVTxPD2DQ_128()
10596 # undef CVT in dis_CVTxPD2DQ_128()
10642 # define CVT(_t) binop( Iop_F64toI32S, \ in dis_CVTxPD2DQ_256() macro
10647 putXMMRegLane32( rG, 3, CVT(t3) ); in dis_CVTxPD2DQ_256()
10648 putXMMRegLane32( rG, 2, CVT(t2) ); in dis_CVTxPD2DQ_256()
10649 putXMMRegLane32( rG, 1, CVT(t1) ); in dis_CVTxPD2DQ_256()
10650 putXMMRegLane32( rG, 0, CVT(t0) ); in dis_CVTxPD2DQ_256()
10651 # undef CVT in dis_CVTxPD2DQ_256()
10691 # define CVT(_t) binop( Iop_F64toF32, \ in dis_CVTDQ2PS_128() macro
10695 putXMMRegLane32F( rG, 3, CVT(t3) ); in dis_CVTDQ2PS_128()
10696 putXMMRegLane32F( rG, 2, CVT(t2) ); in dis_CVTDQ2PS_128()
10697 putXMMRegLane32F( rG, 1, CVT(t1) ); in dis_CVTDQ2PS_128()
10698 putXMMRegLane32F( rG, 0, CVT(t0) ); in dis_CVTDQ2PS_128()
10699 # undef CVT in dis_CVTDQ2PS_128()
10741 # define CVT(_t) binop( Iop_F64toF32, \ in dis_CVTDQ2PS_256() macro
10745 putYMMRegLane32F( rG, 7, CVT(t7) ); in dis_CVTDQ2PS_256()
10746 putYMMRegLane32F( rG, 6, CVT(t6) ); in dis_CVTDQ2PS_256()
10747 putYMMRegLane32F( rG, 5, CVT(t5) ); in dis_CVTDQ2PS_256()
10748 putYMMRegLane32F( rG, 4, CVT(t4) ); in dis_CVTDQ2PS_256()
10749 putYMMRegLane32F( rG, 3, CVT(t3) ); in dis_CVTDQ2PS_256()
10750 putYMMRegLane32F( rG, 2, CVT(t2) ); in dis_CVTDQ2PS_256()
10751 putYMMRegLane32F( rG, 1, CVT(t1) ); in dis_CVTDQ2PS_256()
10752 putYMMRegLane32F( rG, 0, CVT(t0) ); in dis_CVTDQ2PS_256()
10753 # undef CVT in dis_CVTDQ2PS_256()
23309 # define CVT(_t) binop( Iop_F64toF32, mkexpr(rmode), \ in dis_CVTPD2PS_256() macro
23311 putXMMRegLane32F( rG, 3, CVT(t3) ); in dis_CVTPD2PS_256()
23312 putXMMRegLane32F( rG, 2, CVT(t2) ); in dis_CVTPD2PS_256()
23313 putXMMRegLane32F( rG, 1, CVT(t1) ); in dis_CVTPD2PS_256()
23314 putXMMRegLane32F( rG, 0, CVT(t0) ); in dis_CVTPD2PS_256()
23315 # undef CVT in dis_CVTPD2PS_256()
30014 # define CVT(s) binop(Iop_RoundF32toInt, mkexpr(rm), \ in dis_ESC_0F3A__VEX() macro
30016 putYMMRegLane32F( rG, 3, CVT(s3) ); in dis_ESC_0F3A__VEX()
30017 putYMMRegLane32F( rG, 2, CVT(s2) ); in dis_ESC_0F3A__VEX()
30018 putYMMRegLane32F( rG, 1, CVT(s1) ); in dis_ESC_0F3A__VEX()
30019 putYMMRegLane32F( rG, 0, CVT(s0) ); in dis_ESC_0F3A__VEX()
30020 # undef CVT in dis_ESC_0F3A__VEX()
30065 # define CVT(s) binop(Iop_RoundF32toInt, mkexpr(rm), \ in dis_ESC_0F3A__VEX() macro
30067 putYMMRegLane32F( rG, 7, CVT(s7) ); in dis_ESC_0F3A__VEX()
30068 putYMMRegLane32F( rG, 6, CVT(s6) ); in dis_ESC_0F3A__VEX()
30069 putYMMRegLane32F( rG, 5, CVT(s5) ); in dis_ESC_0F3A__VEX()
30070 putYMMRegLane32F( rG, 4, CVT(s4) ); in dis_ESC_0F3A__VEX()
30071 putYMMRegLane32F( rG, 3, CVT(s3) ); in dis_ESC_0F3A__VEX()
30072 putYMMRegLane32F( rG, 2, CVT(s2) ); in dis_ESC_0F3A__VEX()
30073 putYMMRegLane32F( rG, 1, CVT(s1) ); in dis_ESC_0F3A__VEX()
30074 putYMMRegLane32F( rG, 0, CVT(s0) ); in dis_ESC_0F3A__VEX()
30075 # undef CVT in dis_ESC_0F3A__VEX()
30117 # define CVT(s) binop(Iop_RoundF64toInt, mkexpr(rm), \ in dis_ESC_0F3A__VEX() macro
30119 putYMMRegLane64F( rG, 1, CVT(s1) ); in dis_ESC_0F3A__VEX()
30120 putYMMRegLane64F( rG, 0, CVT(s0) ); in dis_ESC_0F3A__VEX()
30121 # undef CVT in dis_ESC_0F3A__VEX()
30162 # define CVT(s) binop(Iop_RoundF64toInt, mkexpr(rm), \ in dis_ESC_0F3A__VEX() macro
30164 putYMMRegLane64F( rG, 3, CVT(s3) ); in dis_ESC_0F3A__VEX()
30165 putYMMRegLane64F( rG, 2, CVT(s2) ); in dis_ESC_0F3A__VEX()
30166 putYMMRegLane64F( rG, 1, CVT(s1) ); in dis_ESC_0F3A__VEX()
30167 putYMMRegLane64F( rG, 0, CVT(s0) ); in dis_ESC_0F3A__VEX()
30168 # undef CVT in dis_ESC_0F3A__VEX()