Lines Matching refs:nLanes
7077 /*OUT*/UInt* nLanes, /*OUT*/Bool* zeroUpper, in getLaneInfo_Q_SZ() argument
7086 if (nLanes) *nLanes = 2; in getLaneInfo_Q_SZ()
7094 if (nLanes) *nLanes = 4; in getLaneInfo_Q_SZ()
7102 if (nLanes) *nLanes = 2; in getLaneInfo_Q_SZ()
10374 UInt nLanes = (isQ ? 128 : 64) / lanebits; in dis_AdvSIMD_shift_by_immediate() local
10378 nameQReg128(dd), nLanes, laneCh, in dis_AdvSIMD_shift_by_immediate()
10379 nameQReg128(nn), nLanes, laneCh, shift); in dis_AdvSIMD_shift_by_immediate()
10417 UInt nLanes = (isQ ? 128 : 64) / lanebits; in dis_AdvSIMD_shift_by_immediate() local
10421 nameQReg128(dd), nLanes, laneCh, in dis_AdvSIMD_shift_by_immediate()
10422 nameQReg128(nn), nLanes, laneCh, shift); in dis_AdvSIMD_shift_by_immediate()
10459 UInt nLanes = (isQ ? 128 : 64) / lanebits; in dis_AdvSIMD_shift_by_immediate() local
10461 nameQReg128(dd), nLanes, laneCh, in dis_AdvSIMD_shift_by_immediate()
10462 nameQReg128(nn), nLanes, laneCh, shift); in dis_AdvSIMD_shift_by_immediate()
10507 UInt nLanes = (isQ ? 128 : 64) / lanebits; in dis_AdvSIMD_shift_by_immediate() local
10510 nameQReg128(dd), nLanes, laneCh, in dis_AdvSIMD_shift_by_immediate()
10511 nameQReg128(nn), nLanes, laneCh, shift); in dis_AdvSIMD_shift_by_immediate()
10734 UInt nLanes = (isQ ? 2 : 1) * (isD ? 1 : 2); in dis_AdvSIMD_shift_by_immediate() local
10735 vassert(nLanes == 2 || nLanes == 4); in dis_AdvSIMD_shift_by_immediate()
10736 for (UInt i = 0; i < nLanes; i++) { in dis_AdvSIMD_shift_by_immediate()
10780 UInt nLanes = (isQ ? 2 : 1) * (isD ? 1 : 2); in dis_AdvSIMD_shift_by_immediate() local
10781 vassert(nLanes == 2 || nLanes == 4); in dis_AdvSIMD_shift_by_immediate()
10782 for (UInt i = 0; i < nLanes; i++) { in dis_AdvSIMD_shift_by_immediate()
12178 UInt nLanes = size == X00 ? 4 : 2; in dis_AdvSIMD_two_reg_misc() local
12182 IRTemp src[nLanes]; in dis_AdvSIMD_two_reg_misc()
12183 for (UInt i = 0; i < nLanes; i++) { in dis_AdvSIMD_two_reg_misc()
12187 for (UInt i = 0; i < nLanes; i++) { in dis_AdvSIMD_two_reg_misc()
12188 putQRegLane(dd, nLanes * bitQ + i, in dis_AdvSIMD_two_reg_misc()
12228 UInt nLanes = size == X00 ? 4 : 2; in dis_AdvSIMD_two_reg_misc() local
12231 IRTemp src[nLanes]; in dis_AdvSIMD_two_reg_misc()
12232 for (UInt i = 0; i < nLanes; i++) { in dis_AdvSIMD_two_reg_misc()
12234 assign(src[i], getQRegLane(nn, nLanes * bitQ + i, srcTy)); in dis_AdvSIMD_two_reg_misc()
12236 for (UInt i = 0; i < nLanes; i++) { in dis_AdvSIMD_two_reg_misc()
12399 UInt nLanes = 0; in dis_AdvSIMD_two_reg_misc() local
12402 Bool ok = getLaneInfo_Q_SZ(&tyI, &tyF, &nLanes, &zeroHI, &arrSpec, in dis_AdvSIMD_two_reg_misc()
12409 for (i = 0; i < nLanes; i++) { in dis_AdvSIMD_two_reg_misc()