1536 static void putQRegLane ( UInt qregNo, UInt laneNo, IRExpr* e )  in putQRegLane()  function
6243                   putQRegLane((tt+3) % 32, ix, loadLE(ty, addr));  in dis_ARM64_load_store()
6253                   putQRegLane((tt+2) % 32, ix, loadLE(ty, addr));  in dis_ARM64_load_store()
6263                   putQRegLane((tt+1) % 32, ix, loadLE(ty, addr));  in dis_ARM64_load_store()
6273                   putQRegLane((tt+0) % 32, ix, loadLE(ty, addr));  in dis_ARM64_load_store()
8667          putQRegLane(dd, laneNo, src);  in dis_AdvSIMD_copy()
8813          putQRegLane(dd, ix1, getQRegLane(nn, ix2, ity));  in dis_AdvSIMD_copy()
9383       putQRegLane(dd, 0, mkexpr(res));  in dis_AdvSIMD_scalar_shift_by_imm()
9385          putQRegLane(dd, 1, mkU32(0));  in dis_AdvSIMD_scalar_shift_by_imm()
9387       putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_scalar_shift_by_imm()
9422       putQRegLane(dd, 0, mkexpr(res));  in dis_AdvSIMD_scalar_shift_by_imm()
9424          putQRegLane(dd, 1, mkU32(0));  in dis_AdvSIMD_scalar_shift_by_imm()
9426       putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_scalar_shift_by_imm()
9663       putQRegLane(dd, 0, mkexpr(res));  in dis_AdvSIMD_scalar_three_same()
9664       putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_scalar_three_same()
10017       putQRegLane(dd, 1, mkU32(0));  in dis_AdvSIMD_scalar_two_reg_misc()
10018       putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_scalar_two_reg_misc()
10064       putQRegLane(dd, 0, mkexpr(res)); /* bits 31-0 or 63-0 */  in dis_AdvSIMD_scalar_two_reg_misc()
10066          putQRegLane(dd, 1, mkU32(0)); /* bits 63-32 */  in dis_AdvSIMD_scalar_two_reg_misc()
10068       putQRegLane(dd, 1, mkU64(0));    /* bits 127-64 */  in dis_AdvSIMD_scalar_two_reg_misc()
10086          putQRegLane(dd, 1, mkU32(0)); /* bits 63-32 */  in dis_AdvSIMD_scalar_two_reg_misc()
10088       putQRegLane(dd, 1, mkU64(0));    /* bits 127-64 */  in dis_AdvSIMD_scalar_two_reg_misc()
10119       putQRegLane(dd, 0, mkexpr(res));  in dis_AdvSIMD_scalar_two_reg_misc()
10744          putQRegLane(dd, i, mkexpr(res));  in dis_AdvSIMD_shift_by_immediate()
10747          putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_shift_by_immediate()
10791          putQRegLane(dd, i, mkexpr(res));  in dis_AdvSIMD_shift_by_immediate()
10794          putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_shift_by_immediate()
12188          putQRegLane(dd, nLanes * bitQ + i,  in dis_AdvSIMD_two_reg_misc()
12192          putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_two_reg_misc()
12213          putQRegLane(dd, 2 * bitQ + i,  in dis_AdvSIMD_two_reg_misc()
12217          putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_two_reg_misc()
12237          putQRegLane(dd, i, unop(opCvt, mkexpr(src[i])));  in dis_AdvSIMD_two_reg_misc()
12295             putQRegLane(dd, i, binop(opRND, mkexpr(irrm),  in dis_AdvSIMD_two_reg_misc()
12301             putQRegLane(dd, i, binop(opRND, mkexpr(irrm),  in dis_AdvSIMD_two_reg_misc()
12305             putQRegLane(dd, 1, mkU64(0)); // zero out lanes 2 and 3  in dis_AdvSIMD_two_reg_misc()
12352             putQRegLane(dd, i, binop(cvt, mkU32(irrm),  in dis_AdvSIMD_two_reg_misc()
12358             putQRegLane(dd, i, binop(cvt, mkU32(irrm),  in dis_AdvSIMD_two_reg_misc()
12362             putQRegLane(dd, 1, mkU64(0)); // zero out lanes 2 and 3  in dis_AdvSIMD_two_reg_misc()
12410             putQRegLane(dd, i,  in dis_AdvSIMD_two_reg_misc()
12414             putQRegLane(dd, 1, mkU64(0));  in dis_AdvSIMD_two_reg_misc()