Lines Matching refs:Min
763 i->Min.LI.dst = dst; in MIPSInstr_LI()
764 i->Min.LI.imm = imm; in MIPSInstr_LI()
772 i->Min.Alu.op = op; in MIPSInstr_Alu()
773 i->Min.Alu.dst = dst; in MIPSInstr_Alu()
774 i->Min.Alu.srcL = srcL; in MIPSInstr_Alu()
775 i->Min.Alu.srcR = srcR; in MIPSInstr_Alu()
784 i->Min.Shft.op = op; in MIPSInstr_Shft()
785 i->Min.Shft.sz32 = sz32; in MIPSInstr_Shft()
786 i->Min.Shft.dst = dst; in MIPSInstr_Shft()
787 i->Min.Shft.srcL = srcL; in MIPSInstr_Shft()
788 i->Min.Shft.srcR = srcR; in MIPSInstr_Shft()
796 i->Min.Unary.op = op; in MIPSInstr_Unary()
797 i->Min.Unary.dst = dst; in MIPSInstr_Unary()
798 i->Min.Unary.src = src; in MIPSInstr_Unary()
807 i->Min.Cmp.syned = syned; in MIPSInstr_Cmp()
808 i->Min.Cmp.sz32 = sz32; in MIPSInstr_Cmp()
809 i->Min.Cmp.dst = dst; in MIPSInstr_Cmp()
810 i->Min.Cmp.srcL = srcL; in MIPSInstr_Cmp()
811 i->Min.Cmp.srcR = srcR; in MIPSInstr_Cmp()
812 i->Min.Cmp.cond = cond; in MIPSInstr_Cmp()
822 i->Min.Mul.syned = syned; in MIPSInstr_Mul()
823 i->Min.Mul.widening = wid; /* widen=True else False */ in MIPSInstr_Mul()
824 i->Min.Mul.sz32 = sz32; /* True = 32 bits */ in MIPSInstr_Mul()
825 i->Min.Mul.dst = dst; in MIPSInstr_Mul()
826 i->Min.Mul.srcL = srcL; in MIPSInstr_Mul()
827 i->Min.Mul.srcR = srcR; in MIPSInstr_Mul()
837 i->Min.Macc.op = Macc_SUB; in MIPSInstr_Msub()
838 i->Min.Macc.syned = syned; in MIPSInstr_Msub()
839 i->Min.Macc.srcL = srcL; in MIPSInstr_Msub()
840 i->Min.Macc.srcR = srcR; in MIPSInstr_Msub()
850 i->Min.Macc.op = Macc_ADD; in MIPSInstr_Madd()
851 i->Min.Macc.syned = syned; in MIPSInstr_Madd()
852 i->Min.Macc.srcL = srcL; in MIPSInstr_Madd()
853 i->Min.Macc.srcR = srcR; in MIPSInstr_Madd()
862 i->Min.Div.syned = syned; in MIPSInstr_Div()
863 i->Min.Div.sz32 = sz32; /* True = 32 bits */ in MIPSInstr_Div()
864 i->Min.Div.srcL = srcL; in MIPSInstr_Div()
865 i->Min.Div.srcR = srcR; in MIPSInstr_Div()
875 i->Min.Call.cond = cond; in MIPSInstr_Call()
876 i->Min.Call.target = target; in MIPSInstr_Call()
877 i->Min.Call.argiregs = argiregs; in MIPSInstr_Call()
878 i->Min.Call.src = src; in MIPSInstr_Call()
879 i->Min.Call.rloc = rloc; in MIPSInstr_Call()
894 i->Min.Call.cond = cond; in MIPSInstr_CallAlways()
895 i->Min.Call.target = target; in MIPSInstr_CallAlways()
896 i->Min.Call.argiregs = argiregs; in MIPSInstr_CallAlways()
897 i->Min.Call.rloc = rloc; in MIPSInstr_CallAlways()
910 i->Min.XDirect.dstGA = dstGA; in MIPSInstr_XDirect()
911 i->Min.XDirect.amPC = amPC; in MIPSInstr_XDirect()
912 i->Min.XDirect.cond = cond; in MIPSInstr_XDirect()
913 i->Min.XDirect.toFastEP = toFastEP; in MIPSInstr_XDirect()
921 i->Min.XIndir.dstGA = dstGA; in MIPSInstr_XIndir()
922 i->Min.XIndir.amPC = amPC; in MIPSInstr_XIndir()
923 i->Min.XIndir.cond = cond; in MIPSInstr_XIndir()
931 i->Min.XAssisted.dstGA = dstGA; in MIPSInstr_XAssisted()
932 i->Min.XAssisted.amPC = amPC; in MIPSInstr_XAssisted()
933 i->Min.XAssisted.cond = cond; in MIPSInstr_XAssisted()
934 i->Min.XAssisted.jk = jk; in MIPSInstr_XAssisted()
942 i->Min.Load.sz = sz; in MIPSInstr_Load()
943 i->Min.Load.src = src; in MIPSInstr_Load()
944 i->Min.Load.dst = dst; in MIPSInstr_Load()
956 i->Min.Store.sz = sz; in MIPSInstr_Store()
957 i->Min.Store.src = src; in MIPSInstr_Store()
958 i->Min.Store.dst = dst; in MIPSInstr_Store()
970 i->Min.LoadL.sz = sz; in MIPSInstr_LoadL()
971 i->Min.LoadL.src = src; in MIPSInstr_LoadL()
972 i->Min.LoadL.dst = dst; in MIPSInstr_LoadL()
985 i->Min.Cas.sz = sz; in MIPSInstr_Cas()
986 i->Min.Cas.old = old; in MIPSInstr_Cas()
987 i->Min.Cas.addr = addr; in MIPSInstr_Cas()
988 i->Min.Cas.expd = expd; in MIPSInstr_Cas()
989 i->Min.Cas.data = data; in MIPSInstr_Cas()
1001 i->Min.StoreC.sz = sz; in MIPSInstr_StoreC()
1002 i->Min.StoreC.src = src; in MIPSInstr_StoreC()
1003 i->Min.StoreC.dst = dst; in MIPSInstr_StoreC()
1015 i->Min.MtHL.src = src; in MIPSInstr_Mthi()
1023 i->Min.MtHL.src = src; in MIPSInstr_Mtlo()
1031 i->Min.MfHL.dst = dst; in MIPSInstr_Mfhi()
1039 i->Min.MfHL.dst = dst; in MIPSInstr_Mflo()
1048 i->Min.RdWrLR.wrLR = wrLR; in MIPSInstr_RdWrLR()
1049 i->Min.RdWrLR.gpr = gpr; in MIPSInstr_RdWrLR()
1057 i->Min.FpLdSt.isLoad = isLoad; in MIPSInstr_FpLdSt()
1058 i->Min.FpLdSt.sz = sz; in MIPSInstr_FpLdSt()
1059 i->Min.FpLdSt.reg = reg; in MIPSInstr_FpLdSt()
1060 i->Min.FpLdSt.addr = addr; in MIPSInstr_FpLdSt()
1069 i->Min.FpUnary.op = op; in MIPSInstr_FpUnary()
1070 i->Min.FpUnary.dst = dst; in MIPSInstr_FpUnary()
1071 i->Min.FpUnary.src = src; in MIPSInstr_FpUnary()
1079 i->Min.FpBinary.op = op; in MIPSInstr_FpBinary()
1080 i->Min.FpBinary.dst = dst; in MIPSInstr_FpBinary()
1081 i->Min.FpBinary.srcL = srcL; in MIPSInstr_FpBinary()
1082 i->Min.FpBinary.srcR = srcR; in MIPSInstr_FpBinary()
1091 i->Min.FpTernary.op = op; in MIPSInstr_FpTernary()
1092 i->Min.FpTernary.dst = dst; in MIPSInstr_FpTernary()
1093 i->Min.FpTernary.src1 = src1; in MIPSInstr_FpTernary()
1094 i->Min.FpTernary.src2 = src2; in MIPSInstr_FpTernary()
1095 i->Min.FpTernary.src3 = src3; in MIPSInstr_FpTernary()
1103 i->Min.FpConvert.op = op; in MIPSInstr_FpConvert()
1104 i->Min.FpConvert.dst = dst; in MIPSInstr_FpConvert()
1105 i->Min.FpConvert.src = src; in MIPSInstr_FpConvert()
1114 i->Min.FpCompare.op = op; in MIPSInstr_FpCompare()
1115 i->Min.FpCompare.dst = dst; in MIPSInstr_FpCompare()
1116 i->Min.FpCompare.srcL = srcL; in MIPSInstr_FpCompare()
1117 i->Min.FpCompare.srcR = srcR; in MIPSInstr_FpCompare()
1125 i->Min.MtFCSR.src = src; in MIPSInstr_MtFCSR()
1133 i->Min.MfFCSR.dst = dst; in MIPSInstr_MfFCSR()
1141 i->Min.FpGpMove.op = op; in MIPSInstr_FpGpMove()
1142 i->Min.FpGpMove.dst = dst; in MIPSInstr_FpGpMove()
1143 i->Min.FpGpMove.src = src; in MIPSInstr_FpGpMove()
1152 i->Min.MoveCond.op = op; in MIPSInstr_MoveCond()
1153 i->Min.MoveCond.dst = dst; in MIPSInstr_MoveCond()
1154 i->Min.MoveCond.src = src; in MIPSInstr_MoveCond()
1155 i->Min.MoveCond.cond = cond; in MIPSInstr_MoveCond()
1163 i->Min.EvCheck.amCounter = amCounter; in MIPSInstr_EvCheck()
1164 i->Min.EvCheck.amFailAddr = amFailAddr; in MIPSInstr_EvCheck()
1186 ppLoadImm(i->Min.LI.dst, i->Min.LI.imm, mode64); in ppMIPSInstr()
1189 HReg r_srcL = i->Min.Alu.srcL; in ppMIPSInstr()
1190 MIPSRH *rh_srcR = i->Min.Alu.srcR; in ppMIPSInstr()
1192 vex_printf("%s ", showMIPSAluOp(i->Min.Alu.op, in ppMIPSInstr()
1194 ppHRegMIPS(i->Min.Alu.dst, mode64); in ppMIPSInstr()
1202 HReg r_srcL = i->Min.Shft.srcL; in ppMIPSInstr()
1203 MIPSRH *rh_srcR = i->Min.Shft.srcR; in ppMIPSInstr()
1204 vex_printf("%s ", showMIPSShftOp(i->Min.Shft.op, in ppMIPSInstr()
1206 i->Min.Shft.sz32)); in ppMIPSInstr()
1207 ppHRegMIPS(i->Min.Shft.dst, mode64); in ppMIPSInstr()
1215 vex_printf("%s ", showMIPSUnaryOp(i->Min.Unary.op)); in ppMIPSInstr()
1216 ppHRegMIPS(i->Min.Unary.dst, mode64); in ppMIPSInstr()
1218 ppHRegMIPS(i->Min.Unary.src, mode64); in ppMIPSInstr()
1223 ppHRegMIPS(i->Min.Cmp.dst, mode64); in ppMIPSInstr()
1224 vex_printf(" = %s ( ", showMIPSCondCode(i->Min.Cmp.cond)); in ppMIPSInstr()
1225 ppHRegMIPS(i->Min.Cmp.srcL, mode64); in ppMIPSInstr()
1227 ppHRegMIPS(i->Min.Cmp.srcR, mode64); in ppMIPSInstr()
1233 switch (i->Min.Mul.widening) { in ppMIPSInstr()
1236 ppHRegMIPS(i->Min.Mul.dst, mode64); in ppMIPSInstr()
1238 ppHRegMIPS(i->Min.Mul.srcL, mode64); in ppMIPSInstr()
1240 ppHRegMIPS(i->Min.Mul.srcR, mode64); in ppMIPSInstr()
1243 vex_printf("%s%s ", i->Min.Mul.sz32 ? "mult" : "dmult", in ppMIPSInstr()
1244 i->Min.Mul.syned ? "" : "u"); in ppMIPSInstr()
1245 ppHRegMIPS(i->Min.Mul.dst, mode64); in ppMIPSInstr()
1247 ppHRegMIPS(i->Min.Mul.srcL, mode64); in ppMIPSInstr()
1249 ppHRegMIPS(i->Min.Mul.srcR, mode64); in ppMIPSInstr()
1256 ppHRegMIPS(i->Min.MtHL.src, mode64); in ppMIPSInstr()
1261 ppHRegMIPS(i->Min.MtHL.src, mode64); in ppMIPSInstr()
1266 ppHRegMIPS(i->Min.MfHL.dst, mode64); in ppMIPSInstr()
1271 ppHRegMIPS(i->Min.MfHL.dst, mode64); in ppMIPSInstr()
1275 vex_printf("%s ", showMIPSMaccOp(i->Min.Macc.op, i->Min.Macc.syned)); in ppMIPSInstr()
1276 ppHRegMIPS(i->Min.Macc.srcL, mode64); in ppMIPSInstr()
1278 ppHRegMIPS(i->Min.Macc.srcR, mode64); in ppMIPSInstr()
1282 if (!i->Min.Div.sz32) in ppMIPSInstr()
1285 vex_printf("%s ", i->Min.Div.syned ? "s" : "u"); in ppMIPSInstr()
1286 ppHRegMIPS(i->Min.Div.srcL, mode64); in ppMIPSInstr()
1288 ppHRegMIPS(i->Min.Div.srcR, mode64); in ppMIPSInstr()
1294 if (i->Min.Call.cond != MIPScc_AL) { in ppMIPSInstr()
1295 vex_printf("if (%s) ", showMIPSCondCode(i->Min.Call.cond)); in ppMIPSInstr()
1301 ppLoadImm(hregMIPS_GPR25(mode64), i->Min.Call.target, mode64); in ppMIPSInstr()
1305 if (i->Min.Call.argiregs & (1 << n)) { in ppMIPSInstr()
1307 if ((i->Min.Call.argiregs >> n) > 1) in ppMIPSInstr()
1320 showMIPSCondCode(i->Min.XDirect.cond)); in ppMIPSInstr()
1321 vex_printf("move $9, 0x%x,", (UInt)i->Min.XDirect.dstGA); in ppMIPSInstr()
1323 ppMIPSAMode(i->Min.XDirect.amPC, mode64); in ppMIPSInstr()
1325 i->Min.XDirect.toFastEP ? "fast" : "slow"); in ppMIPSInstr()
1330 showMIPSCondCode(i->Min.XIndir.cond)); in ppMIPSInstr()
1331 ppHRegMIPS(i->Min.XIndir.dstGA, mode64); in ppMIPSInstr()
1333 ppMIPSAMode(i->Min.XIndir.amPC, mode64); in ppMIPSInstr()
1339 showMIPSCondCode(i->Min.XAssisted.cond)); in ppMIPSInstr()
1341 ppHRegMIPS(i->Min.XAssisted.dstGA, mode64); in ppMIPSInstr()
1343 ppMIPSAMode(i->Min.XAssisted.amPC, mode64); in ppMIPSInstr()
1345 (Int)i->Min.XAssisted.jk); in ppMIPSInstr()
1349 Bool idxd = toBool(i->Min.Load.src->tag == Mam_RR); in ppMIPSInstr()
1350 UChar sz = i->Min.Load.sz; in ppMIPSInstr()
1353 ppHRegMIPS(i->Min.Load.dst, mode64); in ppMIPSInstr()
1355 ppMIPSAMode(i->Min.Load.src, mode64); in ppMIPSInstr()
1359 UChar sz = i->Min.Store.sz; in ppMIPSInstr()
1360 Bool idxd = toBool(i->Min.Store.dst->tag == Mam_RR); in ppMIPSInstr()
1363 ppHRegMIPS(i->Min.Store.src, mode64); in ppMIPSInstr()
1365 ppMIPSAMode(i->Min.Store.dst, mode64); in ppMIPSInstr()
1370 ppHRegMIPS(i->Min.LoadL.dst, mode64); in ppMIPSInstr()
1372 ppMIPSAMode(i->Min.LoadL.src, mode64); in ppMIPSInstr()
1376 Bool sz8 = toBool(i->Min.Cas.sz == 8); in ppMIPSInstr()
1390 ppHRegMIPS(i->Min.Cas.old , mode64); in ppMIPSInstr()
1392 ppHRegMIPS(i->Min.Cas.addr , mode64); in ppMIPSInstr()
1396 ppHRegMIPS(i->Min.Cas.old , mode64); in ppMIPSInstr()
1398 ppHRegMIPS(i->Min.Cas.expd , mode64); in ppMIPSInstr()
1404 ppHRegMIPS(i->Min.Cas.old , mode64); in ppMIPSInstr()
1406 ppHRegMIPS(i->Min.Cas.old , mode64); in ppMIPSInstr()
1410 ppHRegMIPS(i->Min.Cas.data , mode64); in ppMIPSInstr()
1412 ppHRegMIPS(i->Min.Cas.addr , mode64); in ppMIPSInstr()
1416 ppHRegMIPS(i->Min.Cas.old , mode64); in ppMIPSInstr()
1418 ppHRegMIPS(i->Min.Cas.expd , mode64); in ppMIPSInstr()
1420 ppHRegMIPS(i->Min.Cas.data , mode64); in ppMIPSInstr()
1426 ppHRegMIPS(i->Min.StoreC.src, mode64); in ppMIPSInstr()
1428 ppMIPSAMode(i->Min.StoreC.dst, mode64); in ppMIPSInstr()
1432 vex_printf("%s ", i->Min.RdWrLR.wrLR ? "mtlr" : "mflr"); in ppMIPSInstr()
1433 ppHRegMIPS(i->Min.RdWrLR.gpr, mode64); in ppMIPSInstr()
1437 vex_printf("%s ", showMIPSFpOp(i->Min.FpUnary.op)); in ppMIPSInstr()
1438 ppHRegMIPS(i->Min.FpUnary.dst, mode64); in ppMIPSInstr()
1440 ppHRegMIPS(i->Min.FpUnary.src, mode64); in ppMIPSInstr()
1443 vex_printf("%s", showMIPSFpOp(i->Min.FpBinary.op)); in ppMIPSInstr()
1444 ppHRegMIPS(i->Min.FpBinary.dst, mode64); in ppMIPSInstr()
1446 ppHRegMIPS(i->Min.FpBinary.srcL, mode64); in ppMIPSInstr()
1448 ppHRegMIPS(i->Min.FpBinary.srcR, mode64); in ppMIPSInstr()
1451 vex_printf("%s", showMIPSFpOp(i->Min.FpTernary.op)); in ppMIPSInstr()
1452 ppHRegMIPS(i->Min.FpTernary.dst, mode64); in ppMIPSInstr()
1454 ppHRegMIPS(i->Min.FpTernary.src1, mode64); in ppMIPSInstr()
1456 ppHRegMIPS(i->Min.FpTernary.src2, mode64); in ppMIPSInstr()
1458 ppHRegMIPS(i->Min.FpTernary.src3, mode64); in ppMIPSInstr()
1461 vex_printf("%s", showMIPSFpOp(i->Min.FpConvert.op)); in ppMIPSInstr()
1462 ppHRegMIPS(i->Min.FpConvert.dst, mode64); in ppMIPSInstr()
1464 ppHRegMIPS(i->Min.FpConvert.src, mode64); in ppMIPSInstr()
1467 vex_printf("%s ", showMIPSFpOp(i->Min.FpCompare.op)); in ppMIPSInstr()
1468 ppHRegMIPS(i->Min.FpCompare.srcL, mode64); in ppMIPSInstr()
1470 ppHRegMIPS(i->Min.FpCompare.srcR, mode64); in ppMIPSInstr()
1473 vex_printf("%s ", showMIPSFpOp(i->Min.FpMulAcc.op)); in ppMIPSInstr()
1474 ppHRegMIPS(i->Min.FpMulAcc.dst, mode64); in ppMIPSInstr()
1476 ppHRegMIPS(i->Min.FpMulAcc.srcML, mode64); in ppMIPSInstr()
1478 ppHRegMIPS(i->Min.FpMulAcc.srcMR, mode64); in ppMIPSInstr()
1480 ppHRegMIPS(i->Min.FpMulAcc.srcAcc, mode64); in ppMIPSInstr()
1483 if (i->Min.FpLdSt.sz == 4) { in ppMIPSInstr()
1484 if (i->Min.FpLdSt.isLoad) { in ppMIPSInstr()
1486 ppHRegMIPS(i->Min.FpLdSt.reg, mode64); in ppMIPSInstr()
1488 ppMIPSAMode(i->Min.FpLdSt.addr, mode64); in ppMIPSInstr()
1491 ppHRegMIPS(i->Min.FpLdSt.reg, mode64); in ppMIPSInstr()
1493 ppMIPSAMode(i->Min.FpLdSt.addr, mode64); in ppMIPSInstr()
1495 } else if (i->Min.FpLdSt.sz == 8) { in ppMIPSInstr()
1496 if (i->Min.FpLdSt.isLoad) { in ppMIPSInstr()
1498 ppHRegMIPS(i->Min.FpLdSt.reg, mode64); in ppMIPSInstr()
1500 ppMIPSAMode(i->Min.FpLdSt.addr, mode64); in ppMIPSInstr()
1503 ppHRegMIPS(i->Min.FpLdSt.reg, mode64); in ppMIPSInstr()
1505 ppMIPSAMode(i->Min.FpLdSt.addr, mode64); in ppMIPSInstr()
1512 ppHRegMIPS(i->Min.MtFCSR.src, mode64); in ppMIPSInstr()
1518 ppHRegMIPS(i->Min.MfFCSR.dst, mode64); in ppMIPSInstr()
1523 vex_printf("%s ", showMIPSFpGpMoveOp(i->Min.FpGpMove.op)); in ppMIPSInstr()
1524 ppHRegMIPS(i->Min.FpGpMove.dst, mode64); in ppMIPSInstr()
1526 ppHRegMIPS(i->Min.FpGpMove.src, mode64); in ppMIPSInstr()
1530 vex_printf("%s", showMIPSMoveCondOp(i->Min.MoveCond.op)); in ppMIPSInstr()
1531 ppHRegMIPS(i->Min.MoveCond.dst, mode64); in ppMIPSInstr()
1533 ppHRegMIPS(i->Min.MoveCond.src, mode64); in ppMIPSInstr()
1535 ppHRegMIPS(i->Min.MoveCond.cond, mode64); in ppMIPSInstr()
1540 ppMIPSAMode(i->Min.EvCheck.amCounter, mode64); in ppMIPSInstr()
1543 ppMIPSAMode(i->Min.EvCheck.amCounter, mode64); in ppMIPSInstr()
1545 ppMIPSAMode(i->Min.EvCheck.amFailAddr, mode64); in ppMIPSInstr()
1577 addHRegUse(u, HRmWrite, i->Min.LI.dst); in getRegUsage_MIPSInstr()
1580 addHRegUse(u, HRmRead, i->Min.Alu.srcL); in getRegUsage_MIPSInstr()
1581 addRegUsage_MIPSRH(u, i->Min.Alu.srcR); in getRegUsage_MIPSInstr()
1582 addHRegUse(u, HRmWrite, i->Min.Alu.dst); in getRegUsage_MIPSInstr()
1585 addHRegUse(u, HRmRead, i->Min.Shft.srcL); in getRegUsage_MIPSInstr()
1586 addRegUsage_MIPSRH(u, i->Min.Shft.srcR); in getRegUsage_MIPSInstr()
1587 addHRegUse(u, HRmWrite, i->Min.Shft.dst); in getRegUsage_MIPSInstr()
1590 addHRegUse(u, HRmRead, i->Min.Cmp.srcL); in getRegUsage_MIPSInstr()
1591 addHRegUse(u, HRmRead, i->Min.Cmp.srcR); in getRegUsage_MIPSInstr()
1592 addHRegUse(u, HRmWrite, i->Min.Cmp.dst); in getRegUsage_MIPSInstr()
1595 addHRegUse(u, HRmRead, i->Min.Unary.src); in getRegUsage_MIPSInstr()
1596 addHRegUse(u, HRmWrite, i->Min.Unary.dst); in getRegUsage_MIPSInstr()
1599 addHRegUse(u, HRmWrite, i->Min.Mul.dst); in getRegUsage_MIPSInstr()
1600 addHRegUse(u, HRmRead, i->Min.Mul.srcL); in getRegUsage_MIPSInstr()
1601 addHRegUse(u, HRmRead, i->Min.Mul.srcR); in getRegUsage_MIPSInstr()
1607 addHRegUse(u, HRmRead, i->Min.MtHL.src); in getRegUsage_MIPSInstr()
1613 addHRegUse(u, HRmWrite, i->Min.MfHL.dst); in getRegUsage_MIPSInstr()
1616 addHRegUse(u, HRmRead, i->Min.MtFCSR.src); in getRegUsage_MIPSInstr()
1619 addHRegUse(u, HRmWrite, i->Min.MfFCSR.dst); in getRegUsage_MIPSInstr()
1624 addHRegUse(u, HRmRead, i->Min.Macc.srcL); in getRegUsage_MIPSInstr()
1625 addHRegUse(u, HRmRead, i->Min.Macc.srcR); in getRegUsage_MIPSInstr()
1630 addHRegUse(u, HRmRead, i->Min.Div.srcL); in getRegUsage_MIPSInstr()
1631 addHRegUse(u, HRmRead, i->Min.Div.srcR); in getRegUsage_MIPSInstr()
1637 if (i->Min.Call.cond != MIPScc_AL) in getRegUsage_MIPSInstr()
1638 addHRegUse(u, HRmRead, i->Min.Call.src); in getRegUsage_MIPSInstr()
1665 argir = i->Min.Call.argiregs; in getRegUsage_MIPSInstr()
1687 addRegUsage_MIPSAMode(u, i->Min.XDirect.amPC); in getRegUsage_MIPSInstr()
1690 addHRegUse(u, HRmRead, i->Min.XIndir.dstGA); in getRegUsage_MIPSInstr()
1691 addRegUsage_MIPSAMode(u, i->Min.XIndir.amPC); in getRegUsage_MIPSInstr()
1694 addHRegUse(u, HRmRead, i->Min.XAssisted.dstGA); in getRegUsage_MIPSInstr()
1695 addRegUsage_MIPSAMode(u, i->Min.XAssisted.amPC); in getRegUsage_MIPSInstr()
1698 addRegUsage_MIPSAMode(u, i->Min.Load.src); in getRegUsage_MIPSInstr()
1699 addHRegUse(u, HRmWrite, i->Min.Load.dst); in getRegUsage_MIPSInstr()
1702 addHRegUse(u, HRmRead, i->Min.Store.src); in getRegUsage_MIPSInstr()
1703 addRegUsage_MIPSAMode(u, i->Min.Store.dst); in getRegUsage_MIPSInstr()
1706 addRegUsage_MIPSAMode(u, i->Min.LoadL.src); in getRegUsage_MIPSInstr()
1707 addHRegUse(u, HRmWrite, i->Min.LoadL.dst); in getRegUsage_MIPSInstr()
1710 addHRegUse(u, HRmWrite, i->Min.Cas.old); in getRegUsage_MIPSInstr()
1711 addHRegUse(u, HRmRead, i->Min.Cas.addr); in getRegUsage_MIPSInstr()
1712 addHRegUse(u, HRmRead, i->Min.Cas.expd); in getRegUsage_MIPSInstr()
1713 addHRegUse(u, HRmModify, i->Min.Cas.data); in getRegUsage_MIPSInstr()
1716 addHRegUse(u, HRmWrite, i->Min.StoreC.src); in getRegUsage_MIPSInstr()
1717 addHRegUse(u, HRmRead, i->Min.StoreC.src); in getRegUsage_MIPSInstr()
1718 addRegUsage_MIPSAMode(u, i->Min.StoreC.dst); in getRegUsage_MIPSInstr()
1721 addHRegUse(u, (i->Min.RdWrLR.wrLR ? HRmRead : HRmWrite), in getRegUsage_MIPSInstr()
1722 i->Min.RdWrLR.gpr); in getRegUsage_MIPSInstr()
1725 if (i->Min.FpLdSt.sz == 4) { in getRegUsage_MIPSInstr()
1726 addHRegUse(u, (i->Min.FpLdSt.isLoad ? HRmWrite : HRmRead), in getRegUsage_MIPSInstr()
1727 i->Min.FpLdSt.reg); in getRegUsage_MIPSInstr()
1728 addRegUsage_MIPSAMode(u, i->Min.FpLdSt.addr); in getRegUsage_MIPSInstr()
1730 } else if (i->Min.FpLdSt.sz == 8) { in getRegUsage_MIPSInstr()
1731 addHRegUse(u, (i->Min.FpLdSt.isLoad ? HRmWrite : HRmRead), in getRegUsage_MIPSInstr()
1732 i->Min.FpLdSt.reg); in getRegUsage_MIPSInstr()
1733 addRegUsage_MIPSAMode(u, i->Min.FpLdSt.addr); in getRegUsage_MIPSInstr()
1738 addHRegUse(u, HRmWrite, i->Min.FpUnary.dst); in getRegUsage_MIPSInstr()
1739 addHRegUse(u, HRmRead, i->Min.FpUnary.src); in getRegUsage_MIPSInstr()
1742 addHRegUse(u, HRmWrite, i->Min.FpBinary.dst); in getRegUsage_MIPSInstr()
1743 addHRegUse(u, HRmRead, i->Min.FpBinary.srcL); in getRegUsage_MIPSInstr()
1744 addHRegUse(u, HRmRead, i->Min.FpBinary.srcR); in getRegUsage_MIPSInstr()
1747 addHRegUse(u, HRmWrite, i->Min.FpTernary.dst); in getRegUsage_MIPSInstr()
1748 addHRegUse(u, HRmRead, i->Min.FpTernary.src1); in getRegUsage_MIPSInstr()
1749 addHRegUse(u, HRmRead, i->Min.FpTernary.src2); in getRegUsage_MIPSInstr()
1750 addHRegUse(u, HRmRead, i->Min.FpTernary.src3); in getRegUsage_MIPSInstr()
1753 addHRegUse(u, HRmWrite, i->Min.FpConvert.dst); in getRegUsage_MIPSInstr()
1754 addHRegUse(u, HRmRead, i->Min.FpConvert.src); in getRegUsage_MIPSInstr()
1757 addHRegUse(u, HRmWrite, i->Min.FpCompare.dst); in getRegUsage_MIPSInstr()
1758 addHRegUse(u, HRmRead, i->Min.FpCompare.srcL); in getRegUsage_MIPSInstr()
1759 addHRegUse(u, HRmRead, i->Min.FpCompare.srcR); in getRegUsage_MIPSInstr()
1762 addHRegUse(u, HRmWrite, i->Min.FpGpMove.dst); in getRegUsage_MIPSInstr()
1763 addHRegUse(u, HRmRead, i->Min.FpGpMove.src); in getRegUsage_MIPSInstr()
1766 addHRegUse(u, HRmModify, i->Min.MoveCond.dst); in getRegUsage_MIPSInstr()
1767 addHRegUse(u, HRmRead, i->Min.MoveCond.src); in getRegUsage_MIPSInstr()
1768 addHRegUse(u, HRmRead, i->Min.MoveCond.cond); in getRegUsage_MIPSInstr()
1773 addRegUsage_MIPSAMode(u, i->Min.EvCheck.amCounter); in getRegUsage_MIPSInstr()
1774 addRegUsage_MIPSAMode(u, i->Min.EvCheck.amFailAddr); in getRegUsage_MIPSInstr()
1796 mapReg(m, &i->Min.LI.dst); in mapRegs_MIPSInstr()
1799 mapReg(m, &i->Min.Alu.srcL); in mapRegs_MIPSInstr()
1800 mapRegs_MIPSRH(m, i->Min.Alu.srcR); in mapRegs_MIPSInstr()
1801 mapReg(m, &i->Min.Alu.dst); in mapRegs_MIPSInstr()
1804 mapReg(m, &i->Min.Shft.srcL); in mapRegs_MIPSInstr()
1805 mapRegs_MIPSRH(m, i->Min.Shft.srcR); in mapRegs_MIPSInstr()
1806 mapReg(m, &i->Min.Shft.dst); in mapRegs_MIPSInstr()
1809 mapReg(m, &i->Min.Cmp.srcL); in mapRegs_MIPSInstr()
1810 mapReg(m, &i->Min.Cmp.srcR); in mapRegs_MIPSInstr()
1811 mapReg(m, &i->Min.Cmp.dst); in mapRegs_MIPSInstr()
1814 mapReg(m, &i->Min.Unary.src); in mapRegs_MIPSInstr()
1815 mapReg(m, &i->Min.Unary.dst); in mapRegs_MIPSInstr()
1818 mapReg(m, &i->Min.Mul.dst); in mapRegs_MIPSInstr()
1819 mapReg(m, &i->Min.Mul.srcL); in mapRegs_MIPSInstr()
1820 mapReg(m, &i->Min.Mul.srcR); in mapRegs_MIPSInstr()
1824 mapReg(m, &i->Min.MtHL.src); in mapRegs_MIPSInstr()
1828 mapReg(m, &i->Min.MfHL.dst); in mapRegs_MIPSInstr()
1831 mapReg(m, &i->Min.Macc.srcL); in mapRegs_MIPSInstr()
1832 mapReg(m, &i->Min.Macc.srcR); in mapRegs_MIPSInstr()
1835 mapReg(m, &i->Min.Div.srcL); in mapRegs_MIPSInstr()
1836 mapReg(m, &i->Min.Div.srcR); in mapRegs_MIPSInstr()
1840 if (i->Min.Call.cond != MIPScc_AL) in mapRegs_MIPSInstr()
1841 mapReg(m, &i->Min.Call.src); in mapRegs_MIPSInstr()
1845 mapRegs_MIPSAMode(m, i->Min.XDirect.amPC); in mapRegs_MIPSInstr()
1848 mapReg(m, &i->Min.XIndir.dstGA); in mapRegs_MIPSInstr()
1849 mapRegs_MIPSAMode(m, i->Min.XIndir.amPC); in mapRegs_MIPSInstr()
1852 mapReg(m, &i->Min.XAssisted.dstGA); in mapRegs_MIPSInstr()
1853 mapRegs_MIPSAMode(m, i->Min.XAssisted.amPC); in mapRegs_MIPSInstr()
1856 mapRegs_MIPSAMode(m, i->Min.Load.src); in mapRegs_MIPSInstr()
1857 mapReg(m, &i->Min.Load.dst); in mapRegs_MIPSInstr()
1860 mapReg(m, &i->Min.Store.src); in mapRegs_MIPSInstr()
1861 mapRegs_MIPSAMode(m, i->Min.Store.dst); in mapRegs_MIPSInstr()
1864 mapRegs_MIPSAMode(m, i->Min.LoadL.src); in mapRegs_MIPSInstr()
1865 mapReg(m, &i->Min.LoadL.dst); in mapRegs_MIPSInstr()
1868 mapReg(m, &i->Min.Cas.old); in mapRegs_MIPSInstr()
1869 mapReg(m, &i->Min.Cas.addr); in mapRegs_MIPSInstr()
1870 mapReg(m, &i->Min.Cas.expd); in mapRegs_MIPSInstr()
1871 mapReg(m, &i->Min.Cas.data); in mapRegs_MIPSInstr()
1874 mapReg(m, &i->Min.StoreC.src); in mapRegs_MIPSInstr()
1875 mapRegs_MIPSAMode(m, i->Min.StoreC.dst); in mapRegs_MIPSInstr()
1878 mapReg(m, &i->Min.RdWrLR.gpr); in mapRegs_MIPSInstr()
1881 if (i->Min.FpLdSt.sz == 4) { in mapRegs_MIPSInstr()
1882 mapReg(m, &i->Min.FpLdSt.reg); in mapRegs_MIPSInstr()
1883 mapRegs_MIPSAMode(m, i->Min.FpLdSt.addr); in mapRegs_MIPSInstr()
1885 } else if (i->Min.FpLdSt.sz == 8) { in mapRegs_MIPSInstr()
1886 mapReg(m, &i->Min.FpLdSt.reg); in mapRegs_MIPSInstr()
1887 mapRegs_MIPSAMode(m, i->Min.FpLdSt.addr); in mapRegs_MIPSInstr()
1892 mapReg(m, &i->Min.FpUnary.dst); in mapRegs_MIPSInstr()
1893 mapReg(m, &i->Min.FpUnary.src); in mapRegs_MIPSInstr()
1896 mapReg(m, &i->Min.FpBinary.dst); in mapRegs_MIPSInstr()
1897 mapReg(m, &i->Min.FpBinary.srcL); in mapRegs_MIPSInstr()
1898 mapReg(m, &i->Min.FpBinary.srcR); in mapRegs_MIPSInstr()
1901 mapReg(m, &i->Min.FpTernary.dst); in mapRegs_MIPSInstr()
1902 mapReg(m, &i->Min.FpTernary.src1); in mapRegs_MIPSInstr()
1903 mapReg(m, &i->Min.FpTernary.src2); in mapRegs_MIPSInstr()
1904 mapReg(m, &i->Min.FpTernary.src3); in mapRegs_MIPSInstr()
1907 mapReg(m, &i->Min.FpConvert.dst); in mapRegs_MIPSInstr()
1908 mapReg(m, &i->Min.FpConvert.src); in mapRegs_MIPSInstr()
1911 mapReg(m, &i->Min.FpCompare.dst); in mapRegs_MIPSInstr()
1912 mapReg(m, &i->Min.FpCompare.srcL); in mapRegs_MIPSInstr()
1913 mapReg(m, &i->Min.FpCompare.srcR); in mapRegs_MIPSInstr()
1916 mapReg(m, &i->Min.MtFCSR.src); in mapRegs_MIPSInstr()
1919 mapReg(m, &i->Min.MfFCSR.dst); in mapRegs_MIPSInstr()
1922 mapReg(m, &i->Min.FpGpMove.dst); in mapRegs_MIPSInstr()
1923 mapReg(m, &i->Min.FpGpMove.src); in mapRegs_MIPSInstr()
1926 mapReg(m, &i->Min.MoveCond.dst); in mapRegs_MIPSInstr()
1927 mapReg(m, &i->Min.MoveCond.src); in mapRegs_MIPSInstr()
1928 mapReg(m, &i->Min.MoveCond.cond); in mapRegs_MIPSInstr()
1933 mapRegs_MIPSAMode(m, i->Min.EvCheck.amCounter); in mapRegs_MIPSInstr()
1934 mapRegs_MIPSAMode(m, i->Min.EvCheck.amFailAddr); in mapRegs_MIPSInstr()
1956 if (i->Min.Alu.op != Malu_OR) in isMove_MIPSInstr()
1958 if (i->Min.Alu.srcR->tag != Mrh_Reg) in isMove_MIPSInstr()
1960 if (!sameHReg(i->Min.Alu.srcR->Mrh.Reg.reg, i->Min.Alu.srcL)) in isMove_MIPSInstr()
1962 *src = i->Min.Alu.srcL; in isMove_MIPSInstr()
1963 *dst = i->Min.Alu.dst; in isMove_MIPSInstr()
2523 p = mkLoadImm(p, iregNo(i->Min.LI.dst, mode64), i->Min.LI.imm, mode64); in emit_MIPSInstr()
2527 MIPSRH *srcR = i->Min.Alu.srcR; in emit_MIPSInstr()
2529 UInt r_dst = iregNo(i->Min.Alu.dst, mode64); in emit_MIPSInstr()
2530 UInt r_srcL = iregNo(i->Min.Alu.srcL, mode64); in emit_MIPSInstr()
2533 switch (i->Min.Alu.op) { in emit_MIPSInstr()
2639 MIPSRH *srcR = i->Min.Shft.srcR; in emit_MIPSInstr()
2640 Bool sz32 = i->Min.Shft.sz32; in emit_MIPSInstr()
2642 UInt r_dst = iregNo(i->Min.Shft.dst, mode64); in emit_MIPSInstr()
2643 UInt r_srcL = iregNo(i->Min.Shft.srcL, mode64); in emit_MIPSInstr()
2648 switch (i->Min.Shft.op) { in emit_MIPSInstr()
2736 UInt r_dst = iregNo(i->Min.Unary.dst, mode64); in emit_MIPSInstr()
2737 UInt r_src = iregNo(i->Min.Unary.src, mode64); in emit_MIPSInstr()
2739 switch (i->Min.Unary.op) { in emit_MIPSInstr()
2761 UInt r_srcL = iregNo(i->Min.Cmp.srcL, mode64); in emit_MIPSInstr()
2762 UInt r_srcR = iregNo(i->Min.Cmp.srcR, mode64); in emit_MIPSInstr()
2763 UInt r_dst = iregNo(i->Min.Cmp.dst, mode64); in emit_MIPSInstr()
2765 switch (i->Min.Cmp.cond) { in emit_MIPSInstr()
2805 Bool syned = i->Min.Mul.syned; in emit_MIPSInstr()
2806 Bool widening = i->Min.Mul.widening; in emit_MIPSInstr()
2807 Bool sz32 = i->Min.Mul.sz32; in emit_MIPSInstr()
2808 UInt r_srcL = iregNo(i->Min.Mul.srcL, mode64); in emit_MIPSInstr()
2809 UInt r_srcR = iregNo(i->Min.Mul.srcR, mode64); in emit_MIPSInstr()
2810 UInt r_dst = iregNo(i->Min.Mul.dst, mode64); in emit_MIPSInstr()
2838 Bool syned = i->Min.Macc.syned; in emit_MIPSInstr()
2839 UInt r_srcL = iregNo(i->Min.Macc.srcL, mode64); in emit_MIPSInstr()
2840 UInt r_srcR = iregNo(i->Min.Macc.srcR, mode64); in emit_MIPSInstr()
2843 switch (i->Min.Macc.op) { in emit_MIPSInstr()
2857 switch (i->Min.Macc.op) { in emit_MIPSInstr()
2877 Bool syned = i->Min.Div.syned; in emit_MIPSInstr()
2878 Bool sz32 = i->Min.Div.sz32; in emit_MIPSInstr()
2879 UInt r_srcL = iregNo(i->Min.Div.srcL, mode64); in emit_MIPSInstr()
2880 UInt r_srcR = iregNo(i->Min.Div.srcR, mode64); in emit_MIPSInstr()
2901 UInt r_src = iregNo(i->Min.MtHL.src, mode64); in emit_MIPSInstr()
2907 UInt r_src = iregNo(i->Min.MtHL.src, mode64); in emit_MIPSInstr()
2913 UInt r_dst = iregNo(i->Min.MfHL.dst, mode64); in emit_MIPSInstr()
2919 UInt r_dst = iregNo(i->Min.MfHL.dst, mode64); in emit_MIPSInstr()
2925 UInt r_src = iregNo(i->Min.MtFCSR.src, mode64); in emit_MIPSInstr()
2932 UInt r_dst = iregNo(i->Min.MfFCSR.dst, mode64); in emit_MIPSInstr()
2939 if (i->Min.Call.cond != MIPScc_AL in emit_MIPSInstr()
2940 && i->Min.Call.rloc.pri != RLPri_None) { in emit_MIPSInstr()
2950 MIPSCondCode cond = i->Min.Call.cond; in emit_MIPSInstr()
2969 p = mkLoadImm(p, r_dst, i->Min.Call.target, mode64); in emit_MIPSInstr()
2982 UInt r_src = iregNo(i->Min.Call.src, mode64); in emit_MIPSInstr()
3009 if (i->Min.XDirect.cond != MIPScc_AL) { in emit_MIPSInstr()
3010 vassert(i->Min.XDirect.cond != MIPScc_NV); in emit_MIPSInstr()
3018 p = mkLoadImm_EXACTLY2or6(p, /*r*/ 9, (ULong)i->Min.XDirect.dstGA, in emit_MIPSInstr()
3021 i->Min.XDirect.amPC, mode64); in emit_MIPSInstr()
3031 = i->Min.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP in emit_MIPSInstr()
3042 if (i->Min.XDirect.cond != MIPScc_AL) { in emit_MIPSInstr()
3071 if (i->Min.XIndir.cond != MIPScc_AL) { in emit_MIPSInstr()
3072 vassert(i->Min.XIndir.cond != MIPScc_NV); in emit_MIPSInstr()
3080 iregNo(i->Min.XIndir.dstGA, mode64), in emit_MIPSInstr()
3081 i->Min.XIndir.amPC, mode64); in emit_MIPSInstr()
3092 if (i->Min.XIndir.cond != MIPScc_AL) { in emit_MIPSInstr()
3112 if (i->Min.XAssisted.cond != MIPScc_AL) { in emit_MIPSInstr()
3113 vassert(i->Min.XAssisted.cond != MIPScc_NV); in emit_MIPSInstr()
3121 iregNo(i->Min.XIndir.dstGA, mode64), in emit_MIPSInstr()
3122 i->Min.XIndir.amPC, mode64); in emit_MIPSInstr()
3126 switch (i->Min.XAssisted.jk) { in emit_MIPSInstr()
3149 ppIRJumpKind(i->Min.XAssisted.jk); in emit_MIPSInstr()
3164 if (i->Min.XAssisted.cond != MIPScc_AL) { in emit_MIPSInstr()
3180 MIPSAMode *am_addr = i->Min.Load.src; in emit_MIPSInstr()
3182 UInt r_dst = iregNo(i->Min.Load.dst, mode64); in emit_MIPSInstr()
3183 UInt opc, sz = i->Min.Load.sz; in emit_MIPSInstr()
3209 UInt r_dst = iregNo(i->Min.Load.dst, mode64); in emit_MIPSInstr()
3210 UInt opc, sz = i->Min.Load.sz; in emit_MIPSInstr()
3237 MIPSAMode *am_addr = i->Min.Store.dst; in emit_MIPSInstr()
3239 UInt r_src = iregNo(i->Min.Store.src, mode64); in emit_MIPSInstr()
3240 UInt opc, sz = i->Min.Store.sz; in emit_MIPSInstr()
3266 UInt r_src = iregNo(i->Min.Store.src, mode64); in emit_MIPSInstr()
3267 UInt opc, sz = i->Min.Store.sz; in emit_MIPSInstr()
3293 MIPSAMode *am_addr = i->Min.LoadL.src; in emit_MIPSInstr()
3296 UInt r_dst = iregNo(i->Min.LoadL.dst, mode64); in emit_MIPSInstr()
3298 if (i->Min.LoadL.sz == 4) in emit_MIPSInstr()
3305 MIPSAMode *am_addr = i->Min.StoreC.dst; in emit_MIPSInstr()
3306 UInt r_src = iregNo(i->Min.StoreC.src, mode64); in emit_MIPSInstr()
3310 if (i->Min.StoreC.sz == 4) in emit_MIPSInstr()
3317 if (i->Min.Cas.sz != 8 && i->Min.Cas.sz != 4) in emit_MIPSInstr()
3319 UInt old = iregNo(i->Min.Cas.old, mode64); in emit_MIPSInstr()
3320 UInt addr = iregNo(i->Min.Cas.addr, mode64); in emit_MIPSInstr()
3321 UInt expd = iregNo(i->Min.Cas.expd, mode64); in emit_MIPSInstr()
3322 UInt data = iregNo(i->Min.Cas.data, mode64); in emit_MIPSInstr()
3323 Bool sz8 = toBool(i->Min.Cas.sz == 8); in emit_MIPSInstr()
3350 UInt reg = iregNo(i->Min.RdWrLR.gpr, mode64); in emit_MIPSInstr()
3351 Bool wrLR = i->Min.RdWrLR.wrLR; in emit_MIPSInstr()
3361 MIPSAMode *am_addr = i->Min.FpLdSt.addr; in emit_MIPSInstr()
3362 UChar sz = i->Min.FpLdSt.sz; in emit_MIPSInstr()
3365 UInt f_reg = fregNo(i->Min.FpLdSt.reg, mode64); in emit_MIPSInstr()
3366 if (i->Min.FpLdSt.isLoad) { in emit_MIPSInstr()
3378 UInt f_reg = dregNo(i->Min.FpLdSt.reg); in emit_MIPSInstr()
3379 if (i->Min.FpLdSt.isLoad) { in emit_MIPSInstr()
3397 switch (i->Min.FpUnary.op) { in emit_MIPSInstr()
3399 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64); in emit_MIPSInstr()
3400 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64); in emit_MIPSInstr()
3405 UInt fr_dst = dregNo(i->Min.FpUnary.dst); in emit_MIPSInstr()
3406 UInt fr_src = dregNo(i->Min.FpUnary.src); in emit_MIPSInstr()
3411 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64); in emit_MIPSInstr()
3412 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64); in emit_MIPSInstr()
3417 UInt fr_dst = dregNo(i->Min.FpUnary.dst); in emit_MIPSInstr()
3418 UInt fr_src = dregNo(i->Min.FpUnary.src); in emit_MIPSInstr()
3423 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64); in emit_MIPSInstr()
3424 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64); in emit_MIPSInstr()
3429 UInt fr_dst = dregNo(i->Min.FpUnary.dst); in emit_MIPSInstr()
3430 UInt fr_src = dregNo(i->Min.FpUnary.src); in emit_MIPSInstr()
3435 UInt fr_dst = fregNo(i->Min.FpUnary.dst, mode64); in emit_MIPSInstr()
3436 UInt fr_src = fregNo(i->Min.FpUnary.src, mode64); in emit_MIPSInstr()
3441 UInt fr_dst = dregNo(i->Min.FpUnary.dst); in emit_MIPSInstr()
3442 UInt fr_src = dregNo(i->Min.FpUnary.src); in emit_MIPSInstr()
3453 switch (i->Min.FpBinary.op) { in emit_MIPSInstr()
3455 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64); in emit_MIPSInstr()
3456 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64); in emit_MIPSInstr()
3457 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64); in emit_MIPSInstr()
3462 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64); in emit_MIPSInstr()
3463 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64); in emit_MIPSInstr()
3464 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64); in emit_MIPSInstr()
3469 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64); in emit_MIPSInstr()
3470 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64); in emit_MIPSInstr()
3471 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64); in emit_MIPSInstr()
3476 UInt fr_dst = fregNo(i->Min.FpBinary.dst, mode64); in emit_MIPSInstr()
3477 UInt fr_srcL = fregNo(i->Min.FpBinary.srcL, mode64); in emit_MIPSInstr()
3478 UInt fr_srcR = fregNo(i->Min.FpBinary.srcR, mode64); in emit_MIPSInstr()
3483 UInt fr_dst = dregNo(i->Min.FpBinary.dst); in emit_MIPSInstr()
3484 UInt fr_srcL = dregNo(i->Min.FpBinary.srcL); in emit_MIPSInstr()
3485 UInt fr_srcR = dregNo(i->Min.FpBinary.srcR); in emit_MIPSInstr()
3490 UInt fr_dst = dregNo(i->Min.FpBinary.dst); in emit_MIPSInstr()
3491 UInt fr_srcL = dregNo(i->Min.FpBinary.srcL); in emit_MIPSInstr()
3492 UInt fr_srcR = dregNo(i->Min.FpBinary.srcR); in emit_MIPSInstr()
3497 UInt fr_dst = dregNo(i->Min.FpBinary.dst); in emit_MIPSInstr()
3498 UInt fr_srcL = dregNo(i->Min.FpBinary.srcL); in emit_MIPSInstr()
3499 UInt fr_srcR = dregNo(i->Min.FpBinary.srcR); in emit_MIPSInstr()
3504 UInt fr_dst = dregNo(i->Min.FpBinary.dst); in emit_MIPSInstr()
3505 UInt fr_srcL = dregNo(i->Min.FpBinary.srcL); in emit_MIPSInstr()
3506 UInt fr_srcR = dregNo(i->Min.FpBinary.srcR); in emit_MIPSInstr()
3517 switch (i->Min.FpTernary.op) { in emit_MIPSInstr()
3519 UInt fr_dst = fregNo(i->Min.FpTernary.dst, mode64); in emit_MIPSInstr()
3520 UInt fr_src1 = fregNo(i->Min.FpTernary.src1, mode64); in emit_MIPSInstr()
3521 UInt fr_src2 = fregNo(i->Min.FpTernary.src2, mode64); in emit_MIPSInstr()
3522 UInt fr_src3 = fregNo(i->Min.FpTernary.src3, mode64); in emit_MIPSInstr()
3527 UInt fr_dst = dregNo(i->Min.FpTernary.dst); in emit_MIPSInstr()
3528 UInt fr_src1 = dregNo(i->Min.FpTernary.src1); in emit_MIPSInstr()
3529 UInt fr_src2 = dregNo(i->Min.FpTernary.src2); in emit_MIPSInstr()
3530 UInt fr_src3 = dregNo(i->Min.FpTernary.src3); in emit_MIPSInstr()
3535 UInt fr_dst = fregNo(i->Min.FpTernary.dst, mode64); in emit_MIPSInstr()
3536 UInt fr_src1 = fregNo(i->Min.FpTernary.src1, mode64); in emit_MIPSInstr()
3537 UInt fr_src2 = fregNo(i->Min.FpTernary.src2, mode64); in emit_MIPSInstr()
3538 UInt fr_src3 = fregNo(i->Min.FpTernary.src3, mode64); in emit_MIPSInstr()
3543 UInt fr_dst = dregNo(i->Min.FpTernary.dst); in emit_MIPSInstr()
3544 UInt fr_src1 = dregNo(i->Min.FpTernary.src1); in emit_MIPSInstr()
3545 UInt fr_src2 = dregNo(i->Min.FpTernary.src2); in emit_MIPSInstr()
3546 UInt fr_src3 = dregNo(i->Min.FpTernary.src3); in emit_MIPSInstr()
3557 switch (i->Min.FpConvert.op) { in emit_MIPSInstr()
3560 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3561 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3565 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3566 fr_src = fregNo(i->Min.FpConvert.src, mode64); in emit_MIPSInstr()
3570 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3571 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3575 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3576 fr_src = fregNo(i->Min.FpConvert.src, mode64); in emit_MIPSInstr()
3580 fr_dst = dregNo(i->Min.FpConvert.dst); in emit_MIPSInstr()
3581 fr_src = fregNo(i->Min.FpConvert.src, mode64); in emit_MIPSInstr()
3585 fr_dst = dregNo(i->Min.FpConvert.dst); in emit_MIPSInstr()
3586 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3590 fr_dst = dregNo(i->Min.FpConvert.dst); in emit_MIPSInstr()
3591 fr_src = fregNo(i->Min.FpConvert.src, mode64); in emit_MIPSInstr()
3595 fr_dst = dregNo(i->Min.FpConvert.dst); in emit_MIPSInstr()
3596 fr_src = fregNo(i->Min.FpConvert.src, mode64); in emit_MIPSInstr()
3601 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3602 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3604 fr_dst = dregNo(i->Min.FpConvert.dst); in emit_MIPSInstr()
3605 fr_src = fregNo(i->Min.FpConvert.src, mode64); in emit_MIPSInstr()
3610 fr_dst = dregNo(i->Min.FpConvert.dst); in emit_MIPSInstr()
3611 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3615 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3616 fr_src = fregNo(i->Min.FpConvert.src, mode64); in emit_MIPSInstr()
3620 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3621 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3625 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3626 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3630 fr_dst = dregNo(i->Min.FpConvert.dst); in emit_MIPSInstr()
3631 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3635 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3636 fr_src = fregNo(i->Min.FpConvert.src, mode64); in emit_MIPSInstr()
3640 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3641 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3645 fr_dst = dregNo(i->Min.FpConvert.dst); in emit_MIPSInstr()
3646 fr_src = fregNo(i->Min.FpConvert.src, mode64); in emit_MIPSInstr()
3650 fr_dst = dregNo(i->Min.FpConvert.dst); in emit_MIPSInstr()
3651 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3655 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3656 fr_src = fregNo(i->Min.FpConvert.src, mode64); in emit_MIPSInstr()
3660 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3661 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3665 fr_dst = dregNo(i->Min.FpConvert.dst); in emit_MIPSInstr()
3666 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3670 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3671 fr_src = fregNo(i->Min.FpConvert.src, mode64); in emit_MIPSInstr()
3675 fr_dst = fregNo(i->Min.FpConvert.dst, mode64); in emit_MIPSInstr()
3676 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3680 fr_dst = dregNo(i->Min.FpConvert.dst); in emit_MIPSInstr()
3681 fr_src = dregNo(i->Min.FpConvert.src); in emit_MIPSInstr()
3692 UInt r_dst = iregNo(i->Min.FpCompare.dst, mode64); in emit_MIPSInstr()
3693 UInt fr_srcL = dregNo(i->Min.FpCompare.srcL); in emit_MIPSInstr()
3694 UInt fr_srcR = dregNo(i->Min.FpCompare.srcR); in emit_MIPSInstr()
3697 switch (i->Min.FpConvert.op) { in emit_MIPSInstr()
3725 switch (i->Min.FpGpMove.op) { in emit_MIPSInstr()
3728 rt = iregNo(i->Min.FpGpMove.dst, mode64); in emit_MIPSInstr()
3729 fs = fregNo(i->Min.FpGpMove.src, mode64); in emit_MIPSInstr()
3735 rt = iregNo(i->Min.FpGpMove.dst, mode64); in emit_MIPSInstr()
3736 fs = fregNo(i->Min.FpGpMove.src, mode64); in emit_MIPSInstr()
3741 rt = iregNo(i->Min.FpGpMove.src, mode64); in emit_MIPSInstr()
3742 fs = fregNo(i->Min.FpGpMove.dst, mode64); in emit_MIPSInstr()
3748 rt = iregNo(i->Min.FpGpMove.src, mode64); in emit_MIPSInstr()
3749 fs = fregNo(i->Min.FpGpMove.dst, mode64); in emit_MIPSInstr()
3760 switch (i->Min.MoveCond.op) { in emit_MIPSInstr()
3763 d = fregNo(i->Min.MoveCond.dst, mode64); in emit_MIPSInstr()
3764 s = fregNo(i->Min.MoveCond.src, mode64); in emit_MIPSInstr()
3765 t = iregNo(i->Min.MoveCond.cond, mode64); in emit_MIPSInstr()
3770 d = dregNo(i->Min.MoveCond.dst); in emit_MIPSInstr()
3771 s = dregNo(i->Min.MoveCond.src); in emit_MIPSInstr()
3772 t = iregNo(i->Min.MoveCond.cond, mode64); in emit_MIPSInstr()
3777 d = iregNo(i->Min.MoveCond.dst, mode64); in emit_MIPSInstr()
3778 s = iregNo(i->Min.MoveCond.src, mode64); in emit_MIPSInstr()
3779 t = iregNo(i->Min.MoveCond.cond, mode64); in emit_MIPSInstr()
3804 i->Min.EvCheck.amCounter, mode64); in emit_MIPSInstr()
3809 i->Min.EvCheck.amCounter, mode64); in emit_MIPSInstr()
3814 i->Min.EvCheck.amFailAddr, mode64); in emit_MIPSInstr()