137     L1_Hit,   enumerator
318     if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit;  in cachesim_I1_ref()
326     if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit;  in cachesim_D1_ref()
426     if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit;  in cachesim_I1_Read()
438     if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit;  in cachesim_D1_Read()
456 	return L1_Hit;  in cachesim_D1_Write()
533     if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit;  in prefetch_I1_ref()
542     if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit;  in prefetch_D1_ref()
554     if ( cachesim_ref( &I1, a, size) == Hit ) return L1_Hit;  in prefetch_I1_Read()
567     if ( cachesim_ref( &D1, a, size) == Hit ) return L1_Hit;  in prefetch_D1_Read()
587 	return L1_Hit;  in prefetch_D1_Write()
717 	return L1_Hit;							    \
734             return L1_Hit;                                                  \
1052     case L1_Hit:    return "L1 Hit ";  in cacheRes()