Lines Matching refs:Miss
133 typedef enum { Hit = 0, Miss, MissDirty } CacheResult; enumerator
279 return Miss; in cachesim_setref()
305 return ((res1 == Miss) || (res2 == Miss)) ? Miss : Hit; in cachesim_ref()
388 return (tmp_tag & CACHELINE_DIRTY) ? MissDirty : Miss; in cachesim_setref_wb()
413 return ((res1 == Miss) || (res2 == Miss)) ? Miss : Hit; in cachesim_ref_wb()
429 case Miss: return MemAccess; in cachesim_I1_Read()
441 case Miss: return MemAccess; in cachesim_D1_Read()
460 case Miss: return MemAccess; in cachesim_D1_Write()
558 case Miss: return MemAccess; in prefetch_I1_Read()
571 case Miss: return MemAccess; in prefetch_D1_Read()
591 case Miss: return MemAccess; in prefetch_D1_Write()