50 add_cache(VexCacheInfo *ci, VexCache cache)  in add_cache()  argument
54    if (ci->num_caches == num_allocated) {  in add_cache()
56       ci->caches = VG_(realloc)("m_cache", ci->caches,  in add_cache()
57                                 num_allocated * sizeof *ci->caches);  in add_cache()
60    if (ci->num_levels < cache.level) ci->num_levels = cache.level;  in add_cache()
61    ci->caches[ci->num_caches++] = cache;  in add_cache()
67       add_cache(ci, \
73       add_cache(ci, \
79       add_cache(ci, \
88       add_cache(ci, c); \
113 Intel_cache_info(Int level, VexCacheInfo *ci)  in Intel_cache_info()  argument
145    ci->num_levels = 0;  in Intel_cache_info()
146    ci->num_caches = 0;  in Intel_cache_info()
147    ci->icaches_maintain_coherence = True;  in Intel_cache_info()
148    ci->caches = NULL;  in Intel_cache_info()
411 AMD_cache_info(VexCacheInfo *ci)  in AMD_cache_info()  argument
438    ci->num_levels = 2;  in AMD_cache_info()
439    ci->num_caches = 3;  in AMD_cache_info()
440    ci->icaches_maintain_coherence = True;  in AMD_cache_info()
444       ci->num_levels = 3;  in AMD_cache_info()
445       ci->num_caches = 4;  in AMD_cache_info()
448    ci->caches = VG_(malloc)("m_cache", ci->num_caches * sizeof *ci->caches);  in AMD_cache_info()
454    ci->caches[0] = VEX_CACHE_INIT(DATA_CACHE, 1, size, line_size, assoc);  in AMD_cache_info()
460    ci->caches[1] = VEX_CACHE_INIT(INSN_CACHE, 1, size, line_size, assoc);  in AMD_cache_info()
466    ci->caches[2] = VEX_CACHE_INIT(UNIFIED_CACHE, 2, size, line_size, assoc);  in AMD_cache_info()
477       ci->caches[3] = VEX_CACHE_INIT(UNIFIED_CACHE, 3, size, line_size, assoc);  in AMD_cache_info()
484 get_caches_from_CPUID(VexCacheInfo *ci)  in get_caches_from_CPUID()  argument
502       ret = Intel_cache_info(level, ci);  in get_caches_from_CPUID()
505       ret = AMD_cache_info(ci);  in get_caches_from_CPUID()
509       ci->num_levels = 2;  in get_caches_from_CPUID()
510       ci->num_caches = 3;  in get_caches_from_CPUID()
511       ci->icaches_maintain_coherence = True;  in get_caches_from_CPUID()
512       ci->caches = VG_(malloc)("m_cache", ci->num_caches * sizeof *ci->caches);  in get_caches_from_CPUID()
513       ci->caches[0] = VEX_CACHE_INIT(DATA_CACHE,    1, 64, 16, 16);  in get_caches_from_CPUID()
514       ci->caches[1] = VEX_CACHE_INIT(INSN_CACHE,    1, 64, 16,  4);  in get_caches_from_CPUID()
515       ci->caches[2] = VEX_CACHE_INIT(UNIFIED_CACHE, 2, 64, 16, 16);  in get_caches_from_CPUID()
526    for (i = 0; i < ci->num_caches; ++i) {  in get_caches_from_CPUID()
527       ci->caches[i].sizeB *= 1024;  in get_caches_from_CPUID()
606    VexCacheInfo *ci = &vai->hwcache_info;  in get_cache_info()  local
608    ci->icaches_maintain_coherence = True;  in get_cache_info()
620    ci->num_levels = 0;  in get_cache_info()
621    ci->num_caches = 0;  in get_cache_info()
626       ++ci->num_levels;  in get_cache_info()
630       case 0:  ci->num_caches += 2; break; /* separate data and insn cache */  in get_cache_info()
631       case 1:  ci->num_caches += 1; break; /* only insn cache */  in get_cache_info()
632       case 2:  ci->num_caches += 1; break; /* only data cache */  in get_cache_info()
633       case 3:  ci->num_caches += 1; break; /* unified data and insn cache */  in get_cache_info()
637    ci->caches = VG_(malloc)("m_cache", ci->num_caches * sizeof *ci->caches);  in get_cache_info()
640    for (level = 0; level < ci->num_levels; level++) {  in get_cache_info()
645          ci->caches[i++] = get_cache(level, INSN_CACHE);  in get_cache_info()
646          ci->caches[i++] = get_cache(level, DATA_CACHE);  in get_cache_info()
650          ci->caches[i++] = get_cache(level, INSN_CACHE);  in get_cache_info()
654          ci->caches[i++] = get_cache(level, DATA_CACHE);  in get_cache_info()
658          ci->caches[i++] = get_cache(level, UNIFIED_CACHE);  in get_cache_info()
673 write_cache_info(const VexCacheInfo *ci)  in write_cache_info()  argument
678    VG_(debugLog)(1, "cache", "  #levels = %u\n", ci->num_levels);  in write_cache_info()
679    VG_(debugLog)(1, "cache", "  #caches = %u\n", ci->num_caches);  in write_cache_info()
680    for (i = 0; i < ci->num_caches; ++i) {  in write_cache_info()
681       VexCache *c = ci->caches + i;  in write_cache_info()
699 cache_info_is_sensible(const VexCacheInfo *ci)  in cache_info_is_sensible()  argument
707    for (level = 1; level <= ci->num_levels; ++level) {  in cache_info_is_sensible()
711       for (i = 0; i < ci->num_caches; ++i) {  in cache_info_is_sensible()
712          if (ci->caches[i].level == level) {  in cache_info_is_sensible()
713             switch (ci->caches[i].kind) {  in cache_info_is_sensible()
737    for (level = 2; level <= ci->num_levels; ++level) {  in cache_info_is_sensible()
739       for (i = 0; i < ci->num_caches; ++i) {  in cache_info_is_sensible()
740          if (ci->caches[i].level == level - 1) {  in cache_info_is_sensible()
763    VexCacheInfo *ci = &vai->hwcache_info;  in VG_()  local
768       ok = cache_info_is_sensible(ci);  in VG_()
777       write_cache_info(ci);  /* write out for debugging */  in VG_()
782       ci->num_levels = 0;  in VG_()
783       ci->num_caches = 0;  in VG_()
784       VG_(free)(ci->caches);  in VG_()
785       ci->caches = NULL;  in VG_()