Lines Matching refs:dd
96 <dd>Indicates that the device's CPU supports the VFPv2 instruction set. Most ARMv6 CPUs support
97 this instruction set.</dd>
100 <dd>Indicates that the device's CPU supports the ARMv7-A instruction set as supported by the
103 FPU instruction-set extension.</dd>
106 <dd>Indicates that the device's CPU supports the VFPv3 hardware FPU instruction-set extension.
108 16 hardware double-precision FP registers.</p></dd>
111 <dd> Indicates that the device's CPU supports 32 hardware double-precision FP registers instead of
113 single-precision registers mapped to the same register banks.</dd>
116 <dd>Indicates that the device's CPU supports the ARM Advanced SIMD (NEON) vector instruction set
118 hardware FP registers (shared with the NEON unit).</dd>
121 <dd>Indicates that the device's CPU supports instructions to perform floating-point operations on
122 16-bit registers. This feature is part of the VFPv4 specification.</dd>
125 <dd>Indicates that the device's CPU supports the fused multiply-accumulate extension for the VFP
126 instruction set. Also part of the VFPv4 specification.</dd>
129 <dd>Indicates that the device's CPU supports the fused multiply-accumulate extension for the NEON
130 instruction set. Also part of the VFPv4 specification.</dd>
133 <dd>Indicates that the device's CPU supports integer division in ARM mode. Only available on later-
134 model CPUs, such as Cortex-A15.</dd>
137 <dd>Indicates that the device's CPU supports Integer division in Thumb-2 mode. Only available on
138 later-model CPUs, such as Cortex-A15.</dd>
141 <dd>Indicates that the device's CPU supports an instruction-set extension that adds MMX registers
142 and instructions. This feature is only available on a few XScale- based CPUs.</dd>
145 <dd>Indicates that the device's CPU supports LDREX and STREX instructions available since ARMv6.
147 monitor.</dd>
155 <dd>Indicates that the device's CPU has a Floating Point Unit (FPU). All Android ARM64 devices must
156 support this feature.</dd>
158 <dd>Indicates that the device's CPU has an Advanced SIMD (ASIMD) unit. All Android ARM64 devices
159 must support this feature.</dd>
161 <dd>Indicates that the device's CPU supports {@code AES} instructions.</dd>
163 <dd>Indicates that the device's CPU supports {@code CRC32} instructions.</dd>
165 <dd>Indicates that the device's CPU supports {@code SHA1} instructions.</dd>
167 <dd>Indicates that the device's CPU supports {@code SHA2} instructions.</dd>
169 <dd>Indicates that the device's CPU supports 64-bit {@code PMULL} and {@code PMULL2}
170 instructions.</dd>
178 Indicates that the device's CPU supports the SSSE3 instruction extension set.</dd>
181 <dd>Indicates that the device's CPU supports the {@code POPCNT} instruction.</dd>
184 <dd>Indicates that the device's CPU supports the {@code MOVBE} instruction. This instruction is
185 specific to some Intel IA-32 CPUs, such as Atom.</dd>
201 <dd>Indicates that the CPU executes MIPS Release 6 instructions natively, and supports obsoleted R1…
204 <dd>Indicates that the CPU supports MIPS SIMD Architecture instructions.</dd>