Lines Matching refs:supports

17 detect the target device's CPU family and the optional features it supports. It is designed to work
68 the device supports.</p>
80 <p>The second function returns the set of optional features that the device's CPU supports. Declare
96 <dd>Indicates that the device's CPU supports the VFPv2 instruction set. Most ARMv6 CPUs support
100 <dd>Indicates that the device's CPU supports the ARMv7-A instruction set as supported by the
101 <a href="{@docRoot}ndk/guides/abis.html#v7a">armeabi-v7a</a> ABI. This instruction set supports both
106 <dd>Indicates that the device's CPU supports the VFPv3 hardware FPU instruction-set extension.
111 <dd> Indicates that the device's CPU supports 32 hardware double-precision FP registers instead of
116 <dd>Indicates that the device's CPU supports the ARM Advanced SIMD (NEON) vector instruction set
121 <dd>Indicates that the device's CPU supports instructions to perform floating-point operations on
125 <dd>Indicates that the device's CPU supports the fused multiply-accumulate extension for the VFP
129 <dd>Indicates that the device's CPU supports the fused multiply-accumulate extension for the NEON
133 <dd>Indicates that the device's CPU supports integer division in ARM mode. Only available on later-
137 <dd>Indicates that the device's CPU supports Integer division in Thumb-2 mode. Only available on
141 <dd>Indicates that the device's CPU supports an instruction-set extension that adds MMX registers
145 <dd>Indicates that the device's CPU supports LDREX and STREX instructions available since ARMv6.
161 <dd>Indicates that the device's CPU supports {@code AES} instructions.</dd>
163 <dd>Indicates that the device's CPU supports {@code CRC32} instructions.</dd>
165 <dd>Indicates that the device's CPU supports {@code SHA1} instructions.</dd>
167 <dd>Indicates that the device's CPU supports {@code SHA2} instructions.</dd>
169 <dd>Indicates that the device's CPU supports 64-bit {@code PMULL} and {@code PMULL2}
178 Indicates that the device's CPU supports the SSSE3 instruction extension set.</dd>
181 <dd>Indicates that the device's CPU supports the {@code POPCNT} instruction.</dd>
184 <dd>Indicates that the device's CPU supports the {@code MOVBE} instruction. This instruction is
201 <dd>Indicates that the CPU executes MIPS Release 6 instructions natively, and supports obsoleted R1…
204 <dd>Indicates that the CPU supports MIPS SIMD Architecture instructions.</dd>