Lines Matching refs:i16
1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v…
14 declare <4 x i16> @llvm.arm.neon.vmaxs.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
15 declare <4 x i16> @llvm.arm.neon.vmaxu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
23 declare <4 x i16> @llvm.arm.neon.vmins.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
24 declare <4 x i16> @llvm.arm.neon.vminu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
26 declare <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
27 declare <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
30 declare <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
31 declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
34 declare <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
35 declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
70 define internal <4 x i16> @smear_4s(i16 %in) nounwind readnone alwaysinline {
71 %1 = insertelement <4 x i16> undef, i16 %in, i32 0
72 %2 = insertelement <4 x i16> %1, i16 %in, i32 1
73 %3 = insertelement <4 x i16> %2, i16 %in, i32 2
74 %4 = insertelement <4 x i16> %3, i16 %in, i32 3
75 ret <4 x i16> %4
92 define internal <2 x i16> @smear_2s(i16 %in) nounwind readnone alwaysinline {
93 %1 = insertelement <2 x i16> undef, i16 %in, i32 0
94 %2 = insertelement <2 x i16> %1, i16 %in, i32 1
95 ret <2 x i16> %2
403 define signext i16 @_Z3maxss(i16 signext %v1, i16 signext %v2) nounwind readnone {
404 %1 = icmp sgt i16 %v1, %v2
405 %2 = select i1 %1, i16 %v1, i16 %v2
406 ret i16 %2
409 define <2 x i16> @_Z3maxDv2_sS_(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
410 %1 = sext <2 x i16> %v1 to <2 x i32>
411 %2 = sext <2 x i16> %v2 to <2 x i32>
413 %4 = trunc <2 x i32> %3 to <2 x i16>
414 ret <2 x i16> %4
417 define <3 x i16> @_Z3maxDv3_sS_(<3 x i16> %v1, <3 x i16> %v2) nounwind readnone {
418 %1 = sext <3 x i16> %v1 to <3 x i32>
419 %2 = sext <3 x i16> %v2 to <3 x i32>
424 %7 = trunc <3 x i32> %6 to <3 x i16>
425 ret <3 x i16> %7
428 define <4 x i16> @_Z3maxDv4_sS_(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
429 %1 = sext <4 x i16> %v1 to <4 x i32>
430 %2 = sext <4 x i16> %v2 to <4 x i32>
432 %4 = trunc <4 x i32> %3 to <4 x i16>
433 ret <4 x i16> %4
501 define zeroext i16 @_Z3maxtt(i16 zeroext %v1, i16 zeroext %v2) nounwind readnone {
502 %1 = icmp ugt i16 %v1, %v2
503 %2 = select i1 %1, i16 %v1, i16 %v2
504 ret i16 %2
507 define <2 x i16> @_Z3maxDv2_tS_(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
508 %1 = zext <2 x i16> %v1 to <2 x i32>
509 %2 = zext <2 x i16> %v2 to <2 x i32>
511 %4 = trunc <2 x i32> %3 to <2 x i16>
512 ret <2 x i16> %4
515 define <3 x i16> @_Z3maxDv3_tS_(<3 x i16> %v1, <3 x i16> %v2) nounwind readnone {
516 %1 = zext <3 x i16> %v1 to <3 x i32>
517 %2 = zext <3 x i16> %v2 to <3 x i32>
522 %7 = trunc <3 x i32> %6 to <3 x i16>
523 ret <3 x i16> %7
526 define <4 x i16> @_Z3maxDv4_tS_(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
527 %1 = zext <4 x i16> %v1 to <4 x i32>
528 %2 = zext <4 x i16> %v2 to <4 x i32>
530 %4 = trunc <4 x i32> %3 to <4 x i16>
531 ret <4 x i16> %4
634 define signext i16 @_Z3minss(i16 signext %v1, i16 signext %v2) nounwind readnone {
635 %1 = icmp slt i16 %v1, %v2
636 %2 = select i1 %1, i16 %v1, i16 %v2
637 ret i16 %2
640 define <2 x i16> @_Z3minDv2_sS_(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
641 %1 = sext <2 x i16> %v1 to <2 x i32>
642 %2 = sext <2 x i16> %v2 to <2 x i32>
644 %4 = trunc <2 x i32> %3 to <2 x i16>
645 ret <2 x i16> %4
648 define <3 x i16> @_Z3minDv3_sS_(<3 x i16> %v1, <3 x i16> %v2) nounwind readnone {
649 %1 = sext <3 x i16> %v1 to <3 x i32>
650 %2 = sext <3 x i16> %v2 to <3 x i32>
655 %7 = trunc <3 x i32> %6 to <3 x i16>
656 ret <3 x i16> %7
659 define <4 x i16> @_Z3minDv4_sS_(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
660 %1 = sext <4 x i16> %v1 to <4 x i32>
661 %2 = sext <4 x i16> %v2 to <4 x i32>
663 %4 = trunc <4 x i32> %3 to <4 x i16>
664 ret <4 x i16> %4
732 define zeroext i16 @_Z3mintt(i16 zeroext %v1, i16 zeroext %v2) nounwind readnone {
733 %1 = icmp ult i16 %v1, %v2
734 %2 = select i1 %1, i16 %v1, i16 %v2
735 ret i16 %2
738 define <2 x i16> @_Z3minDv2_tS_(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
739 %1 = zext <2 x i16> %v1 to <2 x i32>
740 %2 = zext <2 x i16> %v2 to <2 x i32>
742 %4 = trunc <2 x i32> %3 to <2 x i16>
743 ret <2 x i16> %4
746 define <3 x i16> @_Z3minDv3_tS_(<3 x i16> %v1, <3 x i16> %v2) nounwind readnone {
747 %1 = zext <3 x i16> %v1 to <3 x i32>
748 %2 = zext <3 x i16> %v2 to <3 x i32>
753 %7 = trunc <3 x i32> %6 to <3 x i16>
754 ret <3 x i16> %7
757 define <4 x i16> @_Z3minDv4_tS_(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
758 %1 = zext <4 x i16> %v1 to <4 x i32>
759 %2 = zext <4 x i16> %v2 to <4 x i32>
761 %4 = trunc <4 x i32> %3 to <4 x i16>
762 ret <4 x i16> %4
858 …; %r1 = tail call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %_y3, <4 x i32> <i32 8, i32 …
859 ; %r2 = trunc <4 x i16> %r1 to <4 x i8>