Lines Matching refs:i8
1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v…
26 declare <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
30 declare <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
34 declare <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
370 define signext i8 @_Z3maxcc(i8 signext %v1, i8 signext %v2) nounwind readnone {
371 %1 = icmp sgt i8 %v1, %v2
372 %2 = select i1 %1, i8 %v1, i8 %v2
373 ret i8 %2
376 define <2 x i8> @_Z3maxDv2_cS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
377 %1 = sext <2 x i8> %v1 to <2 x i32>
378 %2 = sext <2 x i8> %v2 to <2 x i32>
380 %4 = trunc <2 x i32> %3 to <2 x i8>
381 ret <2 x i8> %4
384 define <3 x i8> @_Z3maxDv3_cS_(<3 x i8> %v1, <3 x i8> %v2) nounwind readnone {
385 %1 = sext <3 x i8> %v1 to <3 x i32>
386 %2 = sext <3 x i8> %v2 to <3 x i32>
391 %7 = trunc <3 x i32> %6 to <3 x i8>
392 ret <3 x i8> %7
395 define <4 x i8> @_Z3maxDv4_cS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
396 %1 = sext <4 x i8> %v1 to <4 x i32>
397 %2 = sext <4 x i8> %v2 to <4 x i32>
399 %4 = trunc <4 x i32> %3 to <4 x i8>
400 ret <4 x i8> %4
468 define zeroext i8 @_Z3maxhh(i8 zeroext %v1, i8 zeroext %v2) nounwind readnone {
469 %1 = icmp ugt i8 %v1, %v2
470 %2 = select i1 %1, i8 %v1, i8 %v2
471 ret i8 %2
474 define <2 x i8> @_Z3maxDv2_hS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
475 %1 = zext <2 x i8> %v1 to <2 x i32>
476 %2 = zext <2 x i8> %v2 to <2 x i32>
478 %4 = trunc <2 x i32> %3 to <2 x i8>
479 ret <2 x i8> %4
482 define <3 x i8> @_Z3maxDv3_hS_(<3 x i8> %v1, <3 x i8> %v2) nounwind readnone {
483 %1 = zext <3 x i8> %v1 to <3 x i32>
484 %2 = zext <3 x i8> %v2 to <3 x i32>
489 %7 = trunc <3 x i32> %6 to <3 x i8>
490 ret <3 x i8> %7
493 define <4 x i8> @_Z3maxDv4_hS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
494 %1 = zext <4 x i8> %v1 to <4 x i32>
495 %2 = zext <4 x i8> %v2 to <4 x i32>
497 %4 = trunc <4 x i32> %3 to <4 x i8>
498 ret <4 x i8> %4
601 define signext i8 @_Z3mincc(i8 signext %v1, i8 signext %v2) nounwind readnone {
602 %1 = icmp slt i8 %v1, %v2
603 %2 = select i1 %1, i8 %v1, i8 %v2
604 ret i8 %2
607 define <2 x i8> @_Z3minDv2_cS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
608 %1 = sext <2 x i8> %v1 to <2 x i32>
609 %2 = sext <2 x i8> %v2 to <2 x i32>
611 %4 = trunc <2 x i32> %3 to <2 x i8>
612 ret <2 x i8> %4
615 define <3 x i8> @_Z3minDv3_cS_(<3 x i8> %v1, <3 x i8> %v2) nounwind readnone {
616 %1 = sext <3 x i8> %v1 to <3 x i32>
617 %2 = sext <3 x i8> %v2 to <3 x i32>
622 %7 = trunc <3 x i32> %6 to <3 x i8>
623 ret <3 x i8> %7
626 define <4 x i8> @_Z3minDv4_cS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
627 %1 = sext <4 x i8> %v1 to <4 x i32>
628 %2 = sext <4 x i8> %v2 to <4 x i32>
630 %4 = trunc <4 x i32> %3 to <4 x i8>
631 ret <4 x i8> %4
699 define zeroext i8 @_Z3minhh(i8 zeroext %v1, i8 zeroext %v2) nounwind readnone {
700 %1 = icmp ult i8 %v1, %v2
701 %2 = select i1 %1, i8 %v1, i8 %v2
702 ret i8 %2
705 define <2 x i8> @_Z3minDv2_hS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
706 %1 = zext <2 x i8> %v1 to <2 x i32>
707 %2 = zext <2 x i8> %v2 to <2 x i32>
709 %4 = trunc <2 x i32> %3 to <2 x i8>
710 ret <2 x i8> %4
713 define <3 x i8> @_Z3minDv3_hS_(<3 x i8> %v1, <3 x i8> %v2) nounwind readnone {
714 %1 = zext <3 x i8> %v1 to <3 x i32>
715 %2 = zext <3 x i8> %v2 to <3 x i32>
720 %7 = trunc <3 x i32> %6 to <3 x i8>
721 ret <3 x i8> %7
724 define <4 x i8> @_Z3minDv4_hS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
725 %1 = zext <4 x i8> %v1 to <4 x i32>
726 %2 = zext <4 x i8> %v2 to <4 x i32>
728 %4 = trunc <4 x i32> %3 to <4 x i8>
729 ret <4 x i8> %4
838 define <4 x i8> @_Z18rsYuvToRGBA_uchar4hhh(i8 %pY, i8 %pU, i8 %pV) nounwind readnone alwaysinline {
839 %_sy = zext i8 %pY to i32
840 %_su = zext i8 %pU to i32
841 %_sv = zext i8 %pV to i32
859 ; %r2 = trunc <4 x i16> %r1 to <4 x i8>
860 ; ret <4 x i8> %r2
867 %r4 = trunc <4 x i32> %r3 to <4 x i8>
868 ret <4 x i8> %r4
933 declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
957 %px2 = bitcast float* %px to i8*
958 %xm = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %px2, i32 4) nounwind
961 %py2 = bitcast float* %py to i8*
962 %ym = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %py2, i32 4) nounwind
965 %pz2 = bitcast float* %pz to i8*
966 %zm2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %pz2, i32 4) nounwind
1095 declare <4 x i8> @_Z14convert_uchar4Dv4_f(<4 x float> %in) nounwind readnone
1096 declare <4 x float> @_Z14convert_float4Dv4_h(<4 x i8> %in) nounwind readnone
1099 define <4 x i8> @_Z17rsPackColorTo8888Dv4_f(<4 x float> %color) nounwind readnone {
1106 %v4 = tail call <4 x i8> @_Z14convert_uchar4Dv4_f(<4 x float> %v3) nounwind readnone
1107 ret <4 x i8> %v4
1111 define <4 x i8> @_Z17rsPackColorTo8888Dv3_f(<3 x float> %color) nounwind readnone {
1114 %3 = tail call <4 x i8> @_Z17rsPackColorTo8888Dv4_f(<4 x float> %2) nounwind readnone
1115 ret <4 x i8> %3
1119 define <4 x i8> @_Z17rsPackColorTo8888fff(float %r, float %g, float %b) nounwind readnone {
1124 %5 = tail call <4 x i8> @_Z17rsPackColorTo8888Dv4_f(<4 x float> %4) nounwind readnone
1125 ret <4 x i8> %5
1129 define <4 x i8> @_Z17rsPackColorTo8888ffff(float %r, float %g, float %b, float %a) nounwind readnon…
1134 %5 = tail call <4 x i8> @_Z17rsPackColorTo8888Dv4_f(<4 x float> %4) nounwind readnone
1135 ret <4 x i8> %5