| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.cpp | 320 unsigned BaseReg, in isFrameOffsetLegal()
331 unsigned BaseReg, in materializeFrameBaseRegister()
352 void AArch64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
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| D | AArch64LoadStoreOptimizer.cpp | 501 unsigned BaseReg = FirstMI->getOperand(1).getReg(); in findMatchingInsn() local
723 static bool isMatchingUpdateInsn(MachineInstr *MI, unsigned BaseReg, in isMatchingUpdateInsn()
764 unsigned BaseReg = MemMI->getOperand(1).getReg(); in findMatchingUpdateInsnForward() local
819 unsigned BaseReg = MemMI->getOperand(1).getReg(); in findMatchingUpdateInsnBackward() local
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| D | AArch64StorePairSuppress.cpp | 143 unsigned BaseReg; in runOnMachineFunction() local
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| D | AArch64InstrInfo.cpp | 1315 AArch64InstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg, in getLdStBaseRegImmOfs()
1342 MachineInstr *LdSt, unsigned &BaseReg, int &Offset, int &Width, in getLdStBaseRegImmOfsWidth()
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand() local
226 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is32BitMemOperand() local
241 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is64BitMemOperand() local
372 unsigned BaseReg = Base.getReg(); in EmitMemModRMByte() local
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| /external/llvm/lib/Target/ARM/ |
| D | ThumbRegisterInfo.cpp | 127 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg()
183 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmediate()
423 void ThumbRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
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| D | ARMBaseRegisterInfo.cpp | 568 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
592 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
620 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal()
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| D | Thumb2SizeReduction.cpp | 418 unsigned BaseReg = MI->getOperand(0).getReg(); in ReduceLoadStore() local
440 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
454 unsigned BaseReg = MI->getOperand(1).getReg(); in ReduceLoadStore() local
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| D | Thumb2InstrInfo.cpp | 222 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate()
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| D | ARMLoadStoreOptimizer.cpp | 1454 unsigned BaseReg, bool BaseKill, bool BaseUndef, in InsertLDR_STR()
1480 unsigned BaseReg = BaseOp.getReg(); in FixInvalidRegPairOp() local
1962 unsigned &OddReg, unsigned &BaseReg, in CanFormLdStDWord()
2121 unsigned BaseReg = 0, PredReg = 0; in RescheduleOps() local
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| D | ARMBaseInstrInfo.cpp | 164 unsigned BaseReg = Base.getReg(); in convertToThreeAddress() local
1947 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitARMRegPlusImmediate()
4580 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg, in getInsertSubregLikeInputs()
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| /external/llvm/lib/CodeGen/ |
| D | LocalStackSlotAllocation.cpp | 255 lookupCandidateBaseReg(unsigned BaseReg, in lookupCandidateBaseReg()
330 unsigned BaseReg = 0; in insertFrameReferenceRegisters() local
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| /external/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 238 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printLeaMemReference() local
303 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printIntelMemReference() local
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| D | X86SelectionDAGInfo.cpp | 45 unsigned BaseReg = TRI->getBaseRegister(); in isBaseRegConflictPossible() local
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| D | X86MCInstLower.cpp | 762 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg; in EmitNops() local
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| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 792 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
800 virtual void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
807 virtual bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg, in isFrameOffsetLegal()
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| D | TargetInstrInfo.h | 780 RegSubRegPair &BaseReg, in getInsertSubregLikeInputs()
843 unsigned &BaseReg, unsigned &Offset, in getLdStBaseRegImmOfs()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg(); in sandboxLoadStoreStackChange() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 972 unsigned BaseReg, int FrameIdx, in materializeFrameBaseRegister()
992 void PPCRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg, in resolveFrameIndex()
1017 unsigned BaseReg, in isFrameOffsetLegal()
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86IntelInstPrinter.cpp | 159 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); in printMemReference() local
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| D | X86ATTInstPrinter.cpp | 187 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference() local
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 255 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon720aab8e0111::X86AsmParser::IntelExprStateMachine
799 static bool CheckBaseRegAndIndexReg(unsigned BaseReg, unsigned IndexReg, in CheckBaseRegAndIndexReg()
1013 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg, in CreateMemForInlineAsm()
1287 int BaseReg = SM.getBaseReg(); in ParseIntelBracExpression() local
1886 unsigned BaseReg = 0, IndexReg = 0, Scale = 1; in ParseMemOperand() local
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| D | X86Operand.h | 52 unsigned BaseReg; member
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| /external/clang/lib/StaticAnalyzer/Core/ |
| D | Store.cpp | 274 const MemRegion *BaseReg = in evalDerivedToBase() local
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 547 unsigned BaseReg = 0; in parseMEMOperand() local
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