1 /*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include "codegen_x86.h"
18
19 #include "base/bit_utils.h"
20 #include "base/logging.h"
21 #include "dex/compiler_ir.h"
22 #include "dex/quick/mir_to_lir.h"
23 #include "oat.h"
24 #include "utils.h"
25 #include "x86_lir.h"
26
27 namespace art {
28
29 #define MAX_ASSEMBLER_RETRIES 50
30
31 const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = {
32 { kX8632BitData, kData, IS_UNARY_OP, { 0, 0, 0x00, 0, 0, 0, 0, 4, false }, "data", "0x!0d" },
33 { kX86Bkpt, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xCC, 0, 0, 0, 0, 0, false }, "int 3", "" },
34 { kX86Nop, kNop, NO_OPERAND, { 0, 0, 0x90, 0, 0, 0, 0, 0, false }, "nop", "" },
35
36 #define ENCODING_MAP(opname, mem_use, reg_def, uses_ccodes, \
37 rm8_r8, rm32_r32, \
38 r8_rm8, r32_rm32, \
39 ax8_i8, ax32_i32, \
40 rm8_i8, rm8_i8_modrm, \
41 rm32_i32, rm32_i32_modrm, \
42 rm32_i8, rm32_i8_modrm) \
43 { kX86 ## opname ## 8MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8MR", "[!0r+!1d],!2r" }, \
44 { kX86 ## opname ## 8AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
45 { kX86 ## opname ## 8TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_r8, 0, 0, 0, 0, 0, true }, #opname "8TR", "fs:[!0d],!1r" }, \
46 { kX86 ## opname ## 8RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RR", "!0r,!1r" }, \
47 { kX86 ## opname ## 8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RM", "!0r,[!1r+!2d]" }, \
48 { kX86 ## opname ## 8RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
49 { kX86 ## opname ## 8RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r8_rm8, 0, 0, 0, 0, 0, true }, #opname "8RT", "!0r,fs:[!1d]" }, \
50 { kX86 ## opname ## 8RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, ax8_i8, 1, true }, #opname "8RI", "!0r,!1d" }, \
51 { kX86 ## opname ## 8MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, false}, #opname "8MI", "[!0r+!1d],!2d" }, \
52 { kX86 ## opname ## 8AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, false}, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
53 { kX86 ## opname ## 8TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm8_i8, 0, 0, rm8_i8_modrm, 0, 1, false}, #opname "8TI", "fs:[!0d],!1d" }, \
54 \
55 { kX86 ## opname ## 16MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16MR", "[!0r+!1d],!2r" }, \
56 { kX86 ## opname ## 16AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
57 { kX86 ## opname ## 16TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "16TR", "fs:[!0d],!1r" }, \
58 { kX86 ## opname ## 16RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RR", "!0r,!1r" }, \
59 { kX86 ## opname ## 16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RM", "!0r,[!1r+!2d]" }, \
60 { kX86 ## opname ## 16RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0x66, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
61 { kX86 ## opname ## 16RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "16RT", "!0r,fs:[!1d]" }, \
62 { kX86 ## opname ## 16RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 2, false }, #opname "16RI", "!0r,!1d" }, \
63 { kX86 ## opname ## 16MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16MI", "[!0r+!1d],!2d" }, \
64 { kX86 ## opname ## 16AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
65 { kX86 ## opname ## 16TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i32, 0, 0, rm32_i32_modrm, 0, 2, false }, #opname "16TI", "fs:[!0d],!1d" }, \
66 { kX86 ## opname ## 16RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16RI8", "!0r,!1d" }, \
67 { kX86 ## opname ## 16MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16MI8", "[!0r+!1d],!2d" }, \
68 { kX86 ## opname ## 16AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0x66, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \
69 { kX86 ## opname ## 16TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0x66, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "16TI8", "fs:[!0d],!1d" }, \
70 \
71 { kX86 ## opname ## 32MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32MR", "[!0r+!1d],!2r" }, \
72 { kX86 ## opname ## 32AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
73 { kX86 ## opname ## 32TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "32TR", "fs:[!0d],!1r" }, \
74 { kX86 ## opname ## 32RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RR", "!0r,!1r" }, \
75 { kX86 ## opname ## 32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RM", "!0r,[!1r+!2d]" }, \
76 { kX86 ## opname ## 32RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { 0, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
77 { kX86 ## opname ## 32RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "32RT", "!0r,fs:[!1d]" }, \
78 { kX86 ## opname ## 32RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "32RI", "!0r,!1d" }, \
79 { kX86 ## opname ## 32MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32MI", "[!0r+!1d],!2d" }, \
80 { kX86 ## opname ## 32AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
81 { kX86 ## opname ## 32TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "32TI", "fs:[!0d],!1d" }, \
82 { kX86 ## opname ## 32RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32RI8", "!0r,!1d" }, \
83 { kX86 ## opname ## 32MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32MI8", "[!0r+!1d],!2d" }, \
84 { kX86 ## opname ## 32AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { 0, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \
85 { kX86 ## opname ## 32TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "32TI8", "fs:[!0d],!1d" }, \
86 \
87 { kX86 ## opname ## 64MR, kMemReg, mem_use | IS_TERTIARY_OP | REG_USE02 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64MR", "[!0r+!1d],!2r" }, \
88 { kX86 ## opname ## 64AR, kArrayReg, mem_use | IS_QUIN_OP | REG_USE014 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64AR", "[!0r+!1r<<!2d+!3d],!4r" }, \
89 { kX86 ## opname ## 64TR, kThreadReg, mem_use | IS_BINARY_OP | REG_USE1 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_r32, 0, 0, 0, 0, 0, false }, #opname "64TR", "fs:[!0d],!1r" }, \
90 { kX86 ## opname ## 64RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RR", "!0r,!1r" }, \
91 { kX86 ## opname ## 64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RM", "!0r,[!1r+!2d]" }, \
92 { kX86 ## opname ## 64RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE012 | SETS_CCODES | uses_ccodes, { REX_W, 0, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RA", "!0r,[!1r+!2r<<!3d+!4d]" }, \
93 { kX86 ## opname ## 64RT, kRegThread, IS_LOAD | IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, r32_rm32, 0, 0, 0, 0, 0, false }, #opname "64RT", "!0r,fs:[!1d]" }, \
94 { kX86 ## opname ## 64RI, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, ax32_i32, 4, false }, #opname "64RI", "!0r,!1d" }, \
95 { kX86 ## opname ## 64MI, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64MI", "[!0r+!1d],!2d" }, \
96 { kX86 ## opname ## 64AI, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
97 { kX86 ## opname ## 64TI, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i32, 0, 0, rm32_i32_modrm, 0, 4, false }, #opname "64TI", "fs:[!0d],!1d" }, \
98 { kX86 ## opname ## 64RI8, kRegImm, IS_BINARY_OP | reg_def | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64RI8", "!0r,!1d" }, \
99 { kX86 ## opname ## 64MI8, kMemImm, mem_use | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64MI8", "[!0r+!1d],!2d" }, \
100 { kX86 ## opname ## 64AI8, kArrayImm, mem_use | IS_QUIN_OP | REG_USE01 | SETS_CCODES | uses_ccodes, { REX_W, 0, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64AI8", "[!0r+!1r<<!2d+!3d],!4d" }, \
101 { kX86 ## opname ## 64TI8, kThreadImm, mem_use | IS_BINARY_OP | SETS_CCODES | uses_ccodes, { THREAD_PREFIX, REX_W, rm32_i8, 0, 0, rm32_i8_modrm, 0, 1, false }, #opname "64TI8", "fs:[!0d],!1d" }
102
103 ENCODING_MAP(Add, IS_LOAD | IS_STORE, REG_DEF0, 0,
104 0x00 /* RegMem8/Reg8 */, 0x01 /* RegMem32/Reg32 */,
105 0x02 /* Reg8/RegMem8 */, 0x03 /* Reg32/RegMem32 */,
106 0x04 /* Rax8/imm8 opcode */, 0x05 /* Rax32/imm32 */,
107 0x80, 0x0 /* RegMem8/imm8 */,
108 0x81, 0x0 /* RegMem32/imm32 */, 0x83, 0x0 /* RegMem32/imm8 */),
109 ENCODING_MAP(Or, IS_LOAD | IS_STORE, REG_DEF0, 0,
110 0x08 /* RegMem8/Reg8 */, 0x09 /* RegMem32/Reg32 */,
111 0x0A /* Reg8/RegMem8 */, 0x0B /* Reg32/RegMem32 */,
112 0x0C /* Rax8/imm8 opcode */, 0x0D /* Rax32/imm32 */,
113 0x80, 0x1 /* RegMem8/imm8 */,
114 0x81, 0x1 /* RegMem32/imm32 */, 0x83, 0x1 /* RegMem32/imm8 */),
115 ENCODING_MAP(Adc, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,
116 0x10 /* RegMem8/Reg8 */, 0x11 /* RegMem32/Reg32 */,
117 0x12 /* Reg8/RegMem8 */, 0x13 /* Reg32/RegMem32 */,
118 0x14 /* Rax8/imm8 opcode */, 0x15 /* Rax32/imm32 */,
119 0x80, 0x2 /* RegMem8/imm8 */,
120 0x81, 0x2 /* RegMem32/imm32 */, 0x83, 0x2 /* RegMem32/imm8 */),
121 ENCODING_MAP(Sbb, IS_LOAD | IS_STORE, REG_DEF0, USES_CCODES,
122 0x18 /* RegMem8/Reg8 */, 0x19 /* RegMem32/Reg32 */,
123 0x1A /* Reg8/RegMem8 */, 0x1B /* Reg32/RegMem32 */,
124 0x1C /* Rax8/imm8 opcode */, 0x1D /* Rax32/imm32 */,
125 0x80, 0x3 /* RegMem8/imm8 */,
126 0x81, 0x3 /* RegMem32/imm32 */, 0x83, 0x3 /* RegMem32/imm8 */),
127 ENCODING_MAP(And, IS_LOAD | IS_STORE, REG_DEF0, 0,
128 0x20 /* RegMem8/Reg8 */, 0x21 /* RegMem32/Reg32 */,
129 0x22 /* Reg8/RegMem8 */, 0x23 /* Reg32/RegMem32 */,
130 0x24 /* Rax8/imm8 opcode */, 0x25 /* Rax32/imm32 */,
131 0x80, 0x4 /* RegMem8/imm8 */,
132 0x81, 0x4 /* RegMem32/imm32 */, 0x83, 0x4 /* RegMem32/imm8 */),
133 ENCODING_MAP(Sub, IS_LOAD | IS_STORE, REG_DEF0, 0,
134 0x28 /* RegMem8/Reg8 */, 0x29 /* RegMem32/Reg32 */,
135 0x2A /* Reg8/RegMem8 */, 0x2B /* Reg32/RegMem32 */,
136 0x2C /* Rax8/imm8 opcode */, 0x2D /* Rax32/imm32 */,
137 0x80, 0x5 /* RegMem8/imm8 */,
138 0x81, 0x5 /* RegMem32/imm32 */, 0x83, 0x5 /* RegMem32/imm8 */),
139 ENCODING_MAP(Xor, IS_LOAD | IS_STORE, REG_DEF0, 0,
140 0x30 /* RegMem8/Reg8 */, 0x31 /* RegMem32/Reg32 */,
141 0x32 /* Reg8/RegMem8 */, 0x33 /* Reg32/RegMem32 */,
142 0x34 /* Rax8/imm8 opcode */, 0x35 /* Rax32/imm32 */,
143 0x80, 0x6 /* RegMem8/imm8 */,
144 0x81, 0x6 /* RegMem32/imm32 */, 0x83, 0x6 /* RegMem32/imm8 */),
145 ENCODING_MAP(Cmp, IS_LOAD, 0, 0,
146 0x38 /* RegMem8/Reg8 */, 0x39 /* RegMem32/Reg32 */,
147 0x3A /* Reg8/RegMem8 */, 0x3B /* Reg32/RegMem32 */,
148 0x3C /* Rax8/imm8 opcode */, 0x3D /* Rax32/imm32 */,
149 0x80, 0x7 /* RegMem8/imm8 */,
150 0x81, 0x7 /* RegMem32/imm32 */, 0x83, 0x7 /* RegMem32/imm8 */),
151 #undef ENCODING_MAP
152
153 { kX86Imul16RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RRI", "!0r,!1r,!2d" },
154 { kX86Imul16RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RMI", "!0r,[!1r+!2d],!3d" },
155 { kX86Imul16RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0x66, 0, 0x69, 0, 0, 0, 0, 2, false }, "Imul16RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
156
157 { kX86Imul32RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RRI", "!0r,!1r,!2d" },
158 { kX86Imul32RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RMI", "!0r,[!1r+!2d],!3d" },
159 { kX86Imul32RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul32RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
160 { kX86Imul32RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RRI8", "!0r,!1r,!2d" },
161 { kX86Imul32RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RMI8", "!0r,[!1r+!2d],!3d" },
162 { kX86Imul32RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { 0, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul32RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
163
164 { kX86Imul64RRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RRI", "!0r,!1r,!2d" },
165 { kX86Imul64RMI, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RMI", "!0r,[!1r+!2d],!3d" },
166 { kX86Imul64RAI, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x69, 0, 0, 0, 0, 4, false }, "Imul64RAI", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
167 { kX86Imul64RRI8, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RRI8", "!0r,!1r,!2d" },
168 { kX86Imul64RMI8, kRegMemImm, IS_LOAD | IS_QUAD_OP | REG_DEF0_USE1 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RMI8", "!0r,[!1r+!2d],!3d" },
169 { kX86Imul64RAI8, kRegArrayImm, IS_LOAD | IS_SEXTUPLE_OP | REG_DEF0_USE12 | SETS_CCODES, { REX_W, 0, 0x6B, 0, 0, 0, 0, 1, false }, "Imul64RAI8", "!0r,[!1r+!2r<<!3d+!4d],!5d" },
170
171 { kX86Mov8MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8MR", "[!0r+!1d],!2r" },
172 { kX86Mov8AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8AR", "[!0r+!1r<<!2d+!3d],!4r" },
173 { kX86Mov8TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x88, 0, 0, 0, 0, 0, true }, "Mov8TR", "fs:[!0d],!1r" },
174 { kX86Mov8RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RR", "!0r,!1r" },
175 { kX86Mov8RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RM", "!0r,[!1r+!2d]" },
176 { kX86Mov8RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RA", "!0r,[!1r+!2r<<!3d+!4d]" },
177 { kX86Mov8RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8A, 0, 0, 0, 0, 0, true }, "Mov8RT", "!0r,fs:[!1d]" },
178 { kX86Mov8RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB0, 0, 0, 0, 0, 1, true }, "Mov8RI", "!0r,!1d" },
179 { kX86Mov8MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC6, 0, 0, 0, 0, 1, false}, "Mov8MI", "[!0r+!1d],!2d" },
180 { kX86Mov8AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC6, 0, 0, 0, 0, 1, false}, "Mov8AI", "[!0r+!1r<<!2d+!3d],!4d" },
181 { kX86Mov8TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC6, 0, 0, 0, 0, 1, false}, "Mov8TI", "fs:[!0d],!1d" },
182
183 { kX86Mov16MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16MR", "[!0r+!1d],!2r" },
184 { kX86Mov16AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov16AR", "[!0r+!1r<<!2d+!3d],!4r" },
185 { kX86Mov16TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0x66, 0x89, 0, 0, 0, 0, 0, false }, "Mov16TR", "fs:[!0d],!1r" },
186 { kX86Mov16RR, kRegReg, IS_BINARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RR", "!0r,!1r" },
187 { kX86Mov16RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RM", "!0r,[!1r+!2d]" },
188 { kX86Mov16RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0x66, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RA", "!0r,[!1r+!2r<<!3d+!4d]" },
189 { kX86Mov16RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0x66, 0x8B, 0, 0, 0, 0, 0, false }, "Mov16RT", "!0r,fs:[!1d]" },
190 { kX86Mov16RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0x66, 0, 0xB8, 0, 0, 0, 0, 2, false }, "Mov16RI", "!0r,!1d" },
191 { kX86Mov16MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16MI", "[!0r+!1d],!2d" },
192 { kX86Mov16AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0x66, 0, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16AI", "[!0r+!1r<<!2d+!3d],!4d" },
193 { kX86Mov16TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0x66, 0xC7, 0, 0, 0, 0, 2, false }, "Mov16TI", "fs:[!0d],!1d" },
194
195 { kX86Mov32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32MR", "[!0r+!1d],!2r" },
196 { kX86Mov32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32AR", "[!0r+!1r<<!2d+!3d],!4r" },
197 { kX86Movnti32MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0, 0, 0x0F, 0xC3, 0, 0, 0, 0, false }, "Movnti32MR", "[!0r+!1d],!2r" },
198 { kX86Movnti32AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0, 0, 0x0F, 0xC3, 0, 0, 0, 0, false }, "Movnti32AR", "[!0r+!1r<<!2d+!3d],!4r" },
199 { kX86Mov32TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov32TR", "fs:[!0d],!1r" },
200 { kX86Mov32RR, kRegReg, IS_MOVE | IS_BINARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RR", "!0r,!1r" },
201 { kX86Mov32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RM", "!0r,[!1r+!2d]" },
202 { kX86Mov32RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RA", "!0r,[!1r+!2r<<!3d+!4d]" },
203 { kX86Mov32RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov32RT", "!0r,fs:[!1d]" },
204 { kX86Mov32RI, kMovRegImm, IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "Mov32RI", "!0r,!1d" },
205 { kX86Mov32MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32MI", "[!0r+!1d],!2d" },
206 { kX86Mov32AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { 0, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32AI", "[!0r+!1r<<!2d+!3d],!4d" },
207 { kX86Mov32TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov32TI", "fs:[!0d],!1d" },
208
209 { kX86Lea32RM, kRegMem, IS_TERTIARY_OP | REG_DEF0_USE1, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RM", "!0r,[!1r+!2d]" },
210 { kX86Lea32RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea32RA", "!0r,[!1r+!2r<<!3d+!4d]" },
211
212 { kX86Mov64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64MR", "[!0r+!1d],!2r" },
213 { kX86Mov64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { REX_W, 0, 0x89, 0, 0, 0, 0, 0, false }, "Mov64AR", "[!0r+!1r<<!2d+!3d],!4r" },
214 { kX86Movnti64MR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { REX_W, 0, 0x0F, 0xC3, 0, 0, 0, 0, false }, "Movnti64MR", "[!0r+!1d],!2r" },
215 { kX86Movnti64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { REX_W, 0, 0x0F, 0xC3, 0, 0, 0, 0, false }, "Movnti64AR", "[!0r+!1r<<!2d+!3d],!4r" },
216 { kX86Mov64TR, kThreadReg, IS_STORE | IS_BINARY_OP | REG_USE1, { THREAD_PREFIX, REX_W, 0x89, 0, 0, 0, 0, 0, false }, "Mov64TR", "fs:[!0d],!1r" },
217 { kX86Mov64RR, kRegReg, IS_MOVE | IS_BINARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RR", "!0r,!1r" },
218 { kX86Mov64RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RM", "!0r,[!1r+!2d]" },
219 { kX86Mov64RA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RA", "!0r,[!1r+!2r<<!3d+!4d]" },
220 { kX86Mov64RT, kRegThread, IS_LOAD | IS_BINARY_OP | REG_DEF0, { THREAD_PREFIX, REX_W, 0x8B, 0, 0, 0, 0, 0, false }, "Mov64RT", "!0r,fs:[!1d]" },
221 { kX86Mov64RI32, kRegImm, IS_BINARY_OP | REG_DEF0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64RI32", "!0r,!1d" },
222 { kX86Mov64RI64, kMovRegQuadImm, IS_TERTIARY_OP | REG_DEF0, { REX_W, 0, 0xB8, 0, 0, 0, 0, 8, false }, "Mov64RI64", "!0r,!1q" },
223 { kX86Mov64MI, kMemImm, IS_STORE | IS_TERTIARY_OP | REG_USE0, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64MI", "[!0r+!1d],!2d" },
224 { kX86Mov64AI, kArrayImm, IS_STORE | IS_QUIN_OP | REG_USE01, { REX_W, 0, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64AI", "[!0r+!1r<<!2d+!3d],!4d" },
225 { kX86Mov64TI, kThreadImm, IS_STORE | IS_BINARY_OP, { THREAD_PREFIX, REX_W, 0xC7, 0, 0, 0, 0, 4, false }, "Mov64TI", "fs:[!0d],!1d" },
226
227 { kX86Lea64RM, kRegMem, IS_TERTIARY_OP | REG_DEF0_USE1, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RM", "!0r,[!1r+!2d]" },
228 { kX86Lea64RA, kRegArray, IS_QUIN_OP | REG_DEF0_USE12, { REX_W, 0, 0x8D, 0, 0, 0, 0, 0, false }, "Lea64RA", "!0r,[!1r+!2r<<!3d+!4d]" },
229
230 { kX86Cmov32RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RR", "!2c !0r,!1r" },
231 { kX86Cmov64RRC, kRegRegCond, IS_TERTIARY_OP | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RR", "!2c !0r,!1r" },
232
233 { kX86Cmov32RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc32RM", "!3c !0r,[!1r+!2d]" },
234 { kX86Cmov64RMC, kRegMemCond, IS_QUAD_OP | IS_LOAD | REG_DEF0_USE01 | USES_CCODES, { REX_W, 0, 0x0F, 0x40, 0, 0, 0, 0, false }, "Cmovcc64RM", "!3c !0r,[!1r+!2d]" },
235
236 #define SHIFT_ENCODING_MAP(opname, modrm_opcode) \
237 { kX86 ## opname ## 8RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8RI", "!0r,!1d" }, \
238 { kX86 ## opname ## 8MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8MI", "[!0r+!1d],!2d" }, \
239 { kX86 ## opname ## 8AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC0, 0, 0, modrm_opcode, 0xD1, 1, true }, #opname "8AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
240 { kX86 ## opname ## 8RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8RC", "!0r,cl" }, \
241 { kX86 ## opname ## 8MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8MC", "[!0r+!1d],cl" }, \
242 { kX86 ## opname ## 8AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD2, 0, 0, modrm_opcode, 0, 1, true }, #opname "8AC", "[!0r+!1r<<!2d+!3d],cl" }, \
243 \
244 { kX86 ## opname ## 16RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16RI", "!0r,!1d" }, \
245 { kX86 ## opname ## 16MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16MI", "[!0r+!1d],!2d" }, \
246 { kX86 ## opname ## 16AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "16AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
247 { kX86 ## opname ## 16RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16RC", "!0r,cl" }, \
248 { kX86 ## opname ## 16MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16MC", "[!0r+!1d],cl" }, \
249 { kX86 ## opname ## 16AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0x66, 0, 0xD3, 0, 0, modrm_opcode, 0, 1, false }, #opname "16AC", "[!0r+!1r<<!2d+!3d],cl" }, \
250 \
251 { kX86 ## opname ## 32RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32RI", "!0r,!1d" }, \
252 { kX86 ## opname ## 32MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32MI", "[!0r+!1d],!2d" }, \
253 { kX86 ## opname ## 32AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "32AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
254 { kX86 ## opname ## 32RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32RC", "!0r,cl" }, \
255 { kX86 ## opname ## 32MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32MC", "[!0r+!1d],cl" }, \
256 { kX86 ## opname ## 32AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "32AC", "[!0r+!1r<<!2d+!3d],cl" }, \
257 \
258 { kX86 ## opname ## 64RI, kShiftRegImm, IS_BINARY_OP | REG_DEF0_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64RI", "!0r,!1d" }, \
259 { kX86 ## opname ## 64MI, kShiftMemImm, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64MI", "[!0r+!1d],!2d" }, \
260 { kX86 ## opname ## 64AI, kShiftArrayImm, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xC1, 0, 0, modrm_opcode, 0xD1, 1, false }, #opname "64AI", "[!0r+!1r<<!2d+!3d],!4d" }, \
261 { kX86 ## opname ## 64RC, kShiftRegCl, IS_BINARY_OP | REG_DEF0_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64RC", "!0r,cl" }, \
262 { kX86 ## opname ## 64MC, kShiftMemCl, IS_LOAD | IS_STORE | IS_TERTIARY_OP | REG_USE0 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64MC", "[!0r+!1d],cl" }, \
263 { kX86 ## opname ## 64AC, kShiftArrayCl, IS_LOAD | IS_STORE | IS_QUIN_OP | REG_USE01 | REG_USEC | SETS_CCODES, { REX_W, 0, 0xD3, 0, 0, modrm_opcode, 0, 0, false }, #opname "64AC", "[!0r+!1r<<!2d+!3d],cl" }
264
265 SHIFT_ENCODING_MAP(Rol, 0x0),
266 SHIFT_ENCODING_MAP(Ror, 0x1),
267 SHIFT_ENCODING_MAP(Rcl, 0x2),
268 SHIFT_ENCODING_MAP(Rcr, 0x3),
269 SHIFT_ENCODING_MAP(Sal, 0x4),
270 SHIFT_ENCODING_MAP(Shr, 0x5),
271 SHIFT_ENCODING_MAP(Sar, 0x7),
272 #undef SHIFT_ENCODING_MAP
273
274 { kX86Cmc, kNullary, NO_OPERAND, { 0, 0, 0xF5, 0, 0, 0, 0, 0, false }, "Cmc", "" },
275 { kX86Shld32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32RRI", "!0r,!1r,!2d" },
276 { kX86Shld32RRC, kShiftRegRegCl, IS_TERTIARY_OP | REG_DEF0_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0x0F, 0xA5, 0, 0, 0, 0, false }, "Shld32RRC", "!0r,!1r,cl" },
277 { kX86Shld32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld32MRI", "[!0r+!1d],!2r,!3d" },
278 { kX86Shrd32RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32RRI", "!0r,!1r,!2d" },
279 { kX86Shrd32RRC, kShiftRegRegCl, IS_TERTIARY_OP | REG_DEF0_USE01 | REG_USEC | SETS_CCODES, { 0, 0, 0x0F, 0xAD, 0, 0, 0, 0, false }, "Shrd32RRC", "!0r,!1r,cl" },
280 { kX86Shrd32MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { 0, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd32MRI", "[!0r+!1d],!2r,!3d" },
281 { kX86Shld64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64RRI", "!0r,!1r,!2d" },
282 { kX86Shld64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xA4, 0, 0, 0, 1, false }, "Shld64MRI", "[!0r+!1d],!2r,!3d" },
283 { kX86Shrd64RRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0_USE01 | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64RRI", "!0r,!1r,!2d" },
284 { kX86Shrd64MRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_LOAD | IS_STORE | SETS_CCODES, { REX_W, 0, 0x0F, 0xAC, 0, 0, 0, 1, false }, "Shrd64MRI", "[!0r+!1d],!2r,!3d" },
285
286 { kX86Test8RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8RI", "!0r,!1d" },
287 { kX86Test8MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8MI", "[!0r+!1d],!2d" },
288 { kX86Test8AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF6, 0, 0, 0, 0, 1, true }, "Test8AI", "[!0r+!1r<<!2d+!3d],!4d" },
289 { kX86Test16RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16RI", "!0r,!1d" },
290 { kX86Test16MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16MI", "[!0r+!1d],!2d" },
291 { kX86Test16AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0x66, 0, 0xF7, 0, 0, 0, 0, 2, false }, "Test16AI", "[!0r+!1r<<!2d+!3d],!4d" },
292 { kX86Test32RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32RI", "!0r,!1d" },
293 { kX86Test32MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32MI", "[!0r+!1d],!2d" },
294 { kX86Test32AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test32AI", "[!0r+!1r<<!2d+!3d],!4d" },
295 { kX86Test64RI, kRegImm, IS_BINARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64RI", "!0r,!1d" },
296 { kX86Test64MI, kMemImm, IS_LOAD | IS_TERTIARY_OP | REG_USE0 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64MI", "[!0r+!1d],!2d" },
297 { kX86Test64AI, kArrayImm, IS_LOAD | IS_QUIN_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0xF7, 0, 0, 0, 0, 4, false }, "Test64AI", "[!0r+!1r<<!2d+!3d],!4d" },
298
299 { kX86Test32RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test32RR", "!0r,!1r" },
300 { kX86Test64RR, kRegReg, IS_BINARY_OP | REG_USE01 | SETS_CCODES, { REX_W, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test64RR", "!0r,!1r" },
301 { kX86Test32RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_USE01 | SETS_CCODES, { 0, 0, 0x85, 0, 0, 0, 0, 0, false }, "Test32RM", "!0r,[!1r+!2d]" },
302
303 #define UNARY_ENCODING_MAP(opname, modrm, is_store, sets_ccodes, \
304 reg, reg_kind, reg_flags, \
305 mem, mem_kind, mem_flags, \
306 arr, arr_kind, arr_flags, imm, \
307 b_flags, hw_flags, w_flags, \
308 b_format, hw_format, w_format) \
309 { kX86 ## opname ## 8 ## reg, reg_kind, reg_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #reg, b_format "!0r" }, \
310 { kX86 ## opname ## 8 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #mem, b_format "[!0r+!1d]" }, \
311 { kX86 ## opname ## 8 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | b_flags | sets_ccodes, { 0, 0, 0xF6, 0, 0, modrm, 0, imm << 0, true }, #opname "8" #arr, b_format "[!0r+!1r<<!2d+!3d]" }, \
312 { kX86 ## opname ## 16 ## reg, reg_kind, reg_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #reg, hw_format "!0r" }, \
313 { kX86 ## opname ## 16 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #mem, hw_format "[!0r+!1d]" }, \
314 { kX86 ## opname ## 16 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | hw_flags | sets_ccodes, { 0x66, 0, 0xF7, 0, 0, modrm, 0, imm << 1, false }, #opname "16" #arr, hw_format "[!0r+!1r<<!2d+!3d]" }, \
315 { kX86 ## opname ## 32 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #reg, w_format "!0r" }, \
316 { kX86 ## opname ## 32 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #mem, w_format "[!0r+!1d]" }, \
317 { kX86 ## opname ## 32 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { 0, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "32" #arr, w_format "[!0r+!1r<<!2d+!3d]" }, \
318 { kX86 ## opname ## 64 ## reg, reg_kind, reg_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #reg, w_format "!0r" }, \
319 { kX86 ## opname ## 64 ## mem, mem_kind, IS_LOAD | is_store | mem_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #mem, w_format "[!0r+!1d]" }, \
320 { kX86 ## opname ## 64 ## arr, arr_kind, IS_LOAD | is_store | arr_flags | w_flags | sets_ccodes, { REX_W, 0, 0xF7, 0, 0, modrm, 0, imm << 2, false }, #opname "64" #arr, w_format "[!0r+!1r<<!2d+!3d]" }
321
322 UNARY_ENCODING_MAP(Not, 0x2, IS_STORE, 0, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),
323 UNARY_ENCODING_MAP(Neg, 0x3, IS_STORE, SETS_CCODES, R, kReg, IS_UNARY_OP | REG_DEF0_USE0, M, kMem, IS_BINARY_OP | REG_USE0, A, kArray, IS_QUAD_OP | REG_USE01, 0, 0, 0, 0, "", "", ""),
324
325 UNARY_ENCODING_MAP(Mul, 0x4, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),
326 UNARY_ENCODING_MAP(Imul, 0x5, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEA, REG_DEFAD_USEA, "ax,al,", "dx:ax,ax,", "edx:eax,eax,"),
327 UNARY_ENCODING_MAP(Divmod, 0x6, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),
328 UNARY_ENCODING_MAP(Idivmod, 0x7, 0, SETS_CCODES, DaR, kReg, IS_UNARY_OP | REG_USE0, DaM, kMem, IS_BINARY_OP | REG_USE0, DaA, kArray, IS_QUAD_OP | REG_USE01, 0, REG_DEFA_USEA, REG_DEFAD_USEAD, REG_DEFAD_USEAD, "ah:al,ax,", "dx:ax,dx:ax,", "edx:eax,edx:eax,"),
329 #undef UNARY_ENCODING_MAP
330
331 { kx86Cdq32Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { 0, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cdq", "" },
332 { kx86Cqo64Da, kRegOpcode, NO_OPERAND | REG_DEFAD_USEA, { REX_W, 0, 0x99, 0, 0, 0, 0, 0, false }, "Cqo", "" },
333 { kX86Bswap32R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { 0, 0, 0x0F, 0xC8, 0, 0, 0, 0, false }, "Bswap32R", "!0r" },
334 { kX86Bswap64R, kRegOpcode, IS_UNARY_OP | REG_DEF0_USE0, { REX_W, 0, 0x0F, 0xC8, 0, 0, 0, 0, false }, "Bswap64R", "!0r" },
335 { kX86Push32R, kRegOpcode, IS_UNARY_OP | REG_USE0 | REG_USE_SP | REG_DEF_SP | IS_STORE, { 0, 0, 0x50, 0, 0, 0, 0, 0, false }, "Push32R", "!0r" },
336 { kX86Pop32R, kRegOpcode, IS_UNARY_OP | REG_DEF0 | REG_USE_SP | REG_DEF_SP | IS_LOAD, { 0, 0, 0x58, 0, 0, 0, 0, 0, false }, "Pop32R", "!0r" },
337
338 #define EXT_0F_ENCODING_MAP(opname, prefix, opcode, reg_def) \
339 { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \
340 { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \
341 { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }
342
343 // This is a special encoding with r8_form on the second register only
344 // for Movzx8 and Movsx8.
345 #define EXT_0F_R8_FORM_ENCODING_MAP(opname, prefix, opcode, reg_def) \
346 { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, true }, #opname "RR", "!0r,!1r" }, \
347 { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \
348 { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }
349
350 #define EXT_0F_REX_W_ENCODING_MAP(opname, prefix, opcode, reg_def) \
351 { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \
352 { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \
353 { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, REX_W, 0x0F, opcode, 0, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }
354
355 #define EXT_0F_ENCODING2_MAP(opname, prefix, opcode, opcode2, reg_def) \
356 { kX86 ## opname ## RR, kRegReg, IS_BINARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RR", "!0r,!1r" }, \
357 { kX86 ## opname ## RM, kRegMem, IS_LOAD | IS_TERTIARY_OP | reg_def | REG_USE1, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RM", "!0r,[!1r+!2d]" }, \
358 { kX86 ## opname ## RA, kRegArray, IS_LOAD | IS_QUIN_OP | reg_def | REG_USE12, { prefix, 0, 0x0F, opcode, opcode2, 0, 0, 0, false }, #opname "RA", "!0r,[!1r+!2r<<!3d+!4d]" }
359
360 EXT_0F_ENCODING_MAP(Movsd, 0xF2, 0x10, REG_DEF0),
361 { kX86MovsdMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdMR", "[!0r+!1d],!2r" },
362 { kX86MovsdAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF2, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovsdAR", "[!0r+!1r<<!2d+!3d],!4r" },
363
364 EXT_0F_ENCODING_MAP(Movss, 0xF3, 0x10, REG_DEF0),
365 { kX86MovssMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssMR", "[!0r+!1d],!2r" },
366 { kX86MovssAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0xF3, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovssAR", "[!0r+!1r<<!2d+!3d],!4r" },
367
368 EXT_0F_ENCODING_MAP(Cvtsi2sd, 0xF2, 0x2A, REG_DEF0),
369 EXT_0F_ENCODING_MAP(Cvtsi2ss, 0xF3, 0x2A, REG_DEF0),
370 EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2sd, 0xF2, 0x2A, REG_DEF0),
371 EXT_0F_REX_W_ENCODING_MAP(Cvtsqi2ss, 0xF3, 0x2A, REG_DEF0),
372 EXT_0F_ENCODING_MAP(Cvttsd2si, 0xF2, 0x2C, REG_DEF0),
373 EXT_0F_ENCODING_MAP(Cvttss2si, 0xF3, 0x2C, REG_DEF0),
374 EXT_0F_REX_W_ENCODING_MAP(Cvttsd2sqi, 0xF2, 0x2C, REG_DEF0),
375 EXT_0F_REX_W_ENCODING_MAP(Cvttss2sqi, 0xF3, 0x2C, REG_DEF0),
376 EXT_0F_ENCODING_MAP(Cvtsd2si, 0xF2, 0x2D, REG_DEF0),
377 EXT_0F_ENCODING_MAP(Cvtss2si, 0xF3, 0x2D, REG_DEF0),
378 EXT_0F_ENCODING_MAP(Ucomisd, 0x66, 0x2E, SETS_CCODES|REG_USE0),
379 EXT_0F_ENCODING_MAP(Ucomiss, 0x00, 0x2E, SETS_CCODES|REG_USE0),
380 EXT_0F_ENCODING_MAP(Comisd, 0x66, 0x2F, SETS_CCODES|REG_USE0),
381 EXT_0F_ENCODING_MAP(Comiss, 0x00, 0x2F, SETS_CCODES|REG_USE0),
382 EXT_0F_ENCODING_MAP(Orpd, 0x66, 0x56, REG_DEF0_USE0),
383 EXT_0F_ENCODING_MAP(Orps, 0x00, 0x56, REG_DEF0_USE0),
384 EXT_0F_ENCODING_MAP(Andpd, 0x66, 0x54, REG_DEF0_USE0),
385 EXT_0F_ENCODING_MAP(Andps, 0x00, 0x54, REG_DEF0_USE0),
386 EXT_0F_ENCODING_MAP(Xorpd, 0x66, 0x57, REG_DEF0_USE0),
387 EXT_0F_ENCODING_MAP(Xorps, 0x00, 0x57, REG_DEF0_USE0),
388 EXT_0F_ENCODING_MAP(Addsd, 0xF2, 0x58, REG_DEF0_USE0),
389 EXT_0F_ENCODING_MAP(Addss, 0xF3, 0x58, REG_DEF0_USE0),
390 EXT_0F_ENCODING_MAP(Mulsd, 0xF2, 0x59, REG_DEF0_USE0),
391 EXT_0F_ENCODING_MAP(Mulss, 0xF3, 0x59, REG_DEF0_USE0),
392 EXT_0F_ENCODING_MAP(Cvtsd2ss, 0xF2, 0x5A, REG_DEF0),
393 EXT_0F_ENCODING_MAP(Cvtss2sd, 0xF3, 0x5A, REG_DEF0),
394 EXT_0F_ENCODING_MAP(Subsd, 0xF2, 0x5C, REG_DEF0_USE0),
395 EXT_0F_ENCODING_MAP(Subss, 0xF3, 0x5C, REG_DEF0_USE0),
396 EXT_0F_ENCODING_MAP(Divsd, 0xF2, 0x5E, REG_DEF0_USE0),
397 EXT_0F_ENCODING_MAP(Divss, 0xF3, 0x5E, REG_DEF0_USE0),
398 EXT_0F_ENCODING_MAP(Punpcklbw, 0x66, 0x60, REG_DEF0_USE0),
399 EXT_0F_ENCODING_MAP(Punpcklwd, 0x66, 0x61, REG_DEF0_USE0),
400 EXT_0F_ENCODING_MAP(Punpckldq, 0x66, 0x62, REG_DEF0_USE0),
401 EXT_0F_ENCODING_MAP(Punpcklqdq, 0x66, 0x6C, REG_DEF0_USE0),
402 EXT_0F_ENCODING_MAP(Sqrtsd, 0xF2, 0x51, REG_DEF0_USE0),
403 EXT_0F_ENCODING2_MAP(Pmulld, 0x66, 0x38, 0x40, REG_DEF0_USE0),
404 EXT_0F_ENCODING_MAP(Pmullw, 0x66, 0xD5, REG_DEF0_USE0),
405 EXT_0F_ENCODING_MAP(Pmuludq, 0x66, 0xF4, REG_DEF0_USE0),
406 EXT_0F_ENCODING_MAP(Mulps, 0x00, 0x59, REG_DEF0_USE0),
407 EXT_0F_ENCODING_MAP(Mulpd, 0x66, 0x59, REG_DEF0_USE0),
408 EXT_0F_ENCODING_MAP(Paddb, 0x66, 0xFC, REG_DEF0_USE0),
409 EXT_0F_ENCODING_MAP(Paddw, 0x66, 0xFD, REG_DEF0_USE0),
410 EXT_0F_ENCODING_MAP(Paddd, 0x66, 0xFE, REG_DEF0_USE0),
411 EXT_0F_ENCODING_MAP(Paddq, 0x66, 0xD4, REG_DEF0_USE0),
412 EXT_0F_ENCODING_MAP(Psadbw, 0x66, 0xF6, REG_DEF0_USE0),
413 EXT_0F_ENCODING_MAP(Addps, 0x00, 0x58, REG_DEF0_USE0),
414 EXT_0F_ENCODING_MAP(Addpd, 0x66, 0x58, REG_DEF0_USE0),
415 EXT_0F_ENCODING_MAP(Psubb, 0x66, 0xF8, REG_DEF0_USE0),
416 EXT_0F_ENCODING_MAP(Psubw, 0x66, 0xF9, REG_DEF0_USE0),
417 EXT_0F_ENCODING_MAP(Psubd, 0x66, 0xFA, REG_DEF0_USE0),
418 EXT_0F_ENCODING_MAP(Psubq, 0x66, 0xFB, REG_DEF0_USE0),
419 EXT_0F_ENCODING_MAP(Subps, 0x00, 0x5C, REG_DEF0_USE0),
420 EXT_0F_ENCODING_MAP(Subpd, 0x66, 0x5C, REG_DEF0_USE0),
421 EXT_0F_ENCODING_MAP(Pand, 0x66, 0xDB, REG_DEF0_USE0),
422 EXT_0F_ENCODING_MAP(Por, 0x66, 0xEB, REG_DEF0_USE0),
423 EXT_0F_ENCODING_MAP(Pxor, 0x66, 0xEF, REG_DEF0_USE0),
424 EXT_0F_ENCODING2_MAP(Phaddw, 0x66, 0x38, 0x01, REG_DEF0_USE0),
425 EXT_0F_ENCODING2_MAP(Phaddd, 0x66, 0x38, 0x02, REG_DEF0_USE0),
426 EXT_0F_ENCODING_MAP(Haddpd, 0x66, 0x7C, REG_DEF0_USE0),
427 EXT_0F_ENCODING_MAP(Haddps, 0xF2, 0x7C, REG_DEF0_USE0),
428
429 { kX86PextrbRRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x14, 0, 0, 1, false }, "PextbRRI", "!0r,!1r,!2d" },
430 { kX86PextrwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0xC5, 0x00, 0, 0, 1, false }, "PextwRRI", "!0r,!1r,!2d" },
431 { kX86PextrdRRI, kRegRegImmStore, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "PextdRRI", "!0r,!1r,!2d" },
432 { kX86PextrbMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "PextrbMRI", "[!0r+!1d],!2r,!3d" },
433 { kX86PextrwMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x15, 0, 0, 1, false }, "PextrwMRI", "[!0r+!1d],!2r,!3d" },
434 { kX86PextrdMRI, kMemRegImm, IS_QUAD_OP | REG_USE02 | IS_STORE, { 0x66, 0, 0x0F, 0x3A, 0x16, 0, 0, 1, false }, "PextrdMRI", "[!0r+!1d],!2r,!3d" },
435
436 { kX86PshuflwRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0xF2, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuflwRRI", "!0r,!1r,!2d" },
437 { kX86PshufdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x70, 0, 0, 0, 1, false }, "PshuffRRI", "!0r,!1r,!2d" },
438
439 { kX86ShufpsRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE0 | REG_USE1, { 0x00, 0, 0x0F, 0xC6, 0, 0, 0, 1, false }, "ShufpsRRI", "!0r,!1r,!2d" },
440 { kX86ShufpdRRI, kRegRegImm, IS_TERTIARY_OP | REG_DEF0_USE0 | REG_USE1, { 0x66, 0, 0x0F, 0xC6, 0, 0, 0, 1, false }, "ShufpdRRI", "!0r,!1r,!2d" },
441
442 { kX86PsrawRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 4, 0, 1, false }, "PsrawRI", "!0r,!1d" },
443 { kX86PsradRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 4, 0, 1, false }, "PsradRI", "!0r,!1d" },
444 { kX86PsrlwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 2, 0, 1, false }, "PsrlwRI", "!0r,!1d" },
445 { kX86PsrldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 2, 0, 1, false }, "PsrldRI", "!0r,!1d" },
446 { kX86PsrlqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 2, 0, 1, false }, "PsrlqRI", "!0r,!1d" },
447 { kX86PsrldqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 3, 0, 1, false }, "PsrldqRI", "!0r,!1d" },
448 { kX86PsllwRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x71, 0, 6, 0, 1, false }, "PsllwRI", "!0r,!1d" },
449 { kX86PslldRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x72, 0, 6, 0, 1, false }, "PslldRI", "!0r,!1d" },
450 { kX86PsllqRI, kRegImm, IS_BINARY_OP | REG_DEF0_USE0, { 0x66, 0, 0x0F, 0x73, 0, 6, 0, 1, false }, "PsllqRI", "!0r,!1d" },
451
452 { kX86Fild32M, kMem, IS_LOAD | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDB, 0x00, 0, 0, 0, 0, false }, "Fild32M", "[!0r,!1d]" },
453 { kX86Fild64M, kMem, IS_LOAD | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDF, 0x00, 0, 5, 0, 0, false }, "Fild64M", "[!0r,!1d]" },
454 { kX86Fld32M, kMem, IS_LOAD | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 0, 0, 0, false }, "Fld32M", "[!0r,!1d]" },
455 { kX86Fld64M, kMem, IS_LOAD | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 0, 0, 0, false }, "Fld64M", "[!0r,!1d]" },
456 { kX86Fstp32M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 3, 0, 0, false }, "Fstps32M", "[!0r,!1d]" },
457 { kX86Fstp64M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 3, 0, 0, false }, "Fstpd64M", "[!0r,!1d]" },
458 { kX86Fst32M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xD9, 0x00, 0, 2, 0, 0, false }, "Fsts32M", "[!0r,!1d]" },
459 { kX86Fst64M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | USE_FP_STACK, { 0x0, 0, 0xDD, 0x00, 0, 2, 0, 0, false }, "Fstd64M", "[!0r,!1d]" },
460 { kX86Fprem, kNullary, NO_OPERAND | USE_FP_STACK, { 0xD9, 0, 0xF8, 0, 0, 0, 0, 0, false }, "Fprem64", "" },
461 { kX86Fucompp, kNullary, NO_OPERAND | USE_FP_STACK, { 0xDA, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Fucompp", "" },
462 { kX86Fstsw16R, kNullary, NO_OPERAND | REG_DEFA | USE_FP_STACK, { 0x9B, 0xDF, 0xE0, 0, 0, 0, 0, 0, false }, "Fstsw16R", "ax" },
463
464 EXT_0F_ENCODING_MAP(Movdqa, 0x66, 0x6F, REG_DEF0),
465 { kX86MovdqaMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "MovdqaMR", "[!0r+!1d],!2r" },
466 { kX86MovdqaAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x6F, 0, 0, 0, 0, false }, "MovdqaAR", "[!0r+!1r<<!2d+!3d],!4r" },
467
468
469 EXT_0F_ENCODING_MAP(Movups, 0x0, 0x10, REG_DEF0),
470 { kX86MovupsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsMR", "[!0r+!1d],!2r" },
471 { kX86MovupsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x11, 0, 0, 0, 0, false }, "MovupsAR", "[!0r+!1r<<!2d+!3d],!4r" },
472
473 EXT_0F_ENCODING_MAP(Movaps, 0x0, 0x28, REG_DEF0),
474 { kX86MovapsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsMR", "[!0r+!1d],!2r" },
475 { kX86MovapsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x29, 0, 0, 0, 0, false }, "MovapsAR", "[!0r+!1r<<!2d+!3d],!4r" },
476
477 { kX86MovlpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRM", "!0r,[!1r+!2d]" },
478 { kX86MovlpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x12, 0, 0, 0, 0, false }, "MovlpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },
479 { kX86MovlpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsMR", "[!0r+!1d],!2r" },
480 { kX86MovlpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x13, 0, 0, 0, 0, false }, "MovlpsAR", "[!0r+!1r<<!2d+!3d],!4r" },
481
482 { kX86MovhpsRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE01, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRM", "!0r,[!1r+!2d]" },
483 { kX86MovhpsRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE012, { 0x0, 0, 0x0F, 0x16, 0, 0, 0, 0, false }, "MovhpsRA", "!0r,[!1r+!2r<<!3d+!4d]" },
484 { kX86MovhpsMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsMR", "[!0r+!1d],!2r" },
485 { kX86MovhpsAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x0, 0, 0x0F, 0x17, 0, 0, 0, 0, false }, "MovhpsAR", "[!0r+!1r<<!2d+!3d],!4r" },
486
487 EXT_0F_ENCODING_MAP(Movdxr, 0x66, 0x6E, REG_DEF0),
488 EXT_0F_REX_W_ENCODING_MAP(Movqxr, 0x66, 0x6E, REG_DEF0),
489 { kX86MovqrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxRR", "!0r,!1r" },
490 { kX86MovqrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxMR", "[!0r+!1d],!2r" },
491 { kX86MovqrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, REX_W, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovqrxAR", "[!0r+!1r<<!2d+!3d],!4r" },
492
493 { kX86MovdrxRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE1, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxRR", "!0r,!1r" },
494 { kX86MovdrxMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxMR", "[!0r+!1d],!2r" },
495 { kX86MovdrxAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014, { 0x66, 0, 0x0F, 0x7E, 0, 0, 0, 0, false }, "MovdrxAR", "[!0r+!1r<<!2d+!3d],!4r" },
496
497 { kX86MovsxdRR, kRegReg, IS_BINARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRR", "!0r,!1r" },
498 { kX86MovsxdRM, kRegMem, IS_LOAD | IS_TERTIARY_OP | REG_DEF0 | REG_USE1, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRM", "!0r,[!1r+!2d]" },
499 { kX86MovsxdRA, kRegArray, IS_LOAD | IS_QUIN_OP | REG_DEF0 | REG_USE12, { REX_W, 0, 0x63, 0, 0, 0, 0, 0, false }, "MovsxdRA", "!0r,[!1r+!2r<<!3d+!4d]" },
500
501 { kX86Set8R, kRegCond, IS_BINARY_OP | REG_DEF0 | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, true }, "Set8R", "!1c !0r" },
502 { kX86Set8M, kMemCond, IS_STORE | IS_TERTIARY_OP | REG_USE0 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8M", "!2c [!0r+!1d]" },
503 { kX86Set8A, kArrayCond, IS_STORE | IS_QUIN_OP | REG_USE01 | USES_CCODES, { 0, 0, 0x0F, 0x90, 0, 0, 0, 0, false }, "Set8A", "!4c [!0r+!1r<<!2d+!3d]" },
504
505 // TODO: load/store?
506 // Encode the modrm opcode as an extra opcode byte to avoid computation during assembly.
507 { kX86Lfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 5, 0, 0, false }, "Lfence", "" },
508 { kX86Mfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 6, 0, 0, false }, "Mfence", "" },
509 { kX86Sfence, kReg, NO_OPERAND, { 0, 0, 0x0F, 0xAE, 0, 7, 0, 0, false }, "Sfence", "" },
510
511 EXT_0F_ENCODING_MAP(Imul16, 0x66, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES),
512 EXT_0F_ENCODING_MAP(Imul32, 0x00, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES),
513 EXT_0F_ENCODING_MAP(Imul64, REX_W, 0xAF, REG_USE0 | REG_DEF0 | SETS_CCODES),
514
515 { kX86CmpxchgRR, kRegRegStore, IS_BINARY_OP | REG_DEF0 | REG_USE01 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "!0r,!1r" },
516 { kX86CmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1d],!2r" },
517 { kX86CmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },
518 { kX86LockCmpxchgMR, kMemReg, IS_STORE | IS_TERTIARY_OP | REG_USE02 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1d],!2r" },
519 { kX86LockCmpxchgAR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, 0, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },
520 { kX86LockCmpxchg64AR, kArrayReg, IS_STORE | IS_QUIN_OP | REG_USE014 | REG_DEFA_USEA | SETS_CCODES, { 0xF0, REX_W, 0x0F, 0xB1, 0, 0, 0, 0, false }, "Lock Cmpxchg", "[!0r+!1r<<!2d+!3d],!4r" },
521 { kX86LockCmpxchg64M, kMem, IS_STORE | IS_BINARY_OP | REG_USE0 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1d]" },
522 { kX86LockCmpxchg64A, kArray, IS_STORE | IS_QUAD_OP | REG_USE01 | REG_DEFAD_USEAD | REG_USEC | REG_USEB | SETS_CCODES, { 0xF0, 0, 0x0F, 0xC7, 0, 1, 0, 0, false }, "Lock Cmpxchg8b", "[!0r+!1r<<!2d+!3d]" },
523 { kX86XchgMR, kMemReg, IS_STORE | IS_LOAD | IS_TERTIARY_OP | REG_DEF2 | REG_USE02, { 0, 0, 0x87, 0, 0, 0, 0, 0, false }, "Xchg", "[!0r+!1d],!2r" },
524
525 EXT_0F_R8_FORM_ENCODING_MAP(Movzx8, 0x00, 0xB6, REG_DEF0),
526 EXT_0F_ENCODING_MAP(Movzx16, 0x00, 0xB7, REG_DEF0),
527 EXT_0F_R8_FORM_ENCODING_MAP(Movsx8, 0x00, 0xBE, REG_DEF0),
528 EXT_0F_ENCODING_MAP(Movsx16, 0x00, 0xBF, REG_DEF0),
529 EXT_0F_ENCODING_MAP(Movzx8q, REX_W, 0xB6, REG_DEF0),
530 EXT_0F_ENCODING_MAP(Movzx16q, REX_W, 0xB7, REG_DEF0),
531 EXT_0F_ENCODING_MAP(Movsx8q, REX, 0xBE, REG_DEF0),
532 EXT_0F_ENCODING_MAP(Movsx16q, REX_W, 0xBF, REG_DEF0),
533 #undef EXT_0F_ENCODING_MAP
534
535 { kX86Jcc8, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x70, 0, 0, 0, 0, 0, false }, "Jcc8", "!1c !0t" },
536 { kX86Jcc32, kJcc, IS_BINARY_OP | IS_BRANCH | NEEDS_FIXUP | USES_CCODES, { 0, 0, 0x0F, 0x80, 0, 0, 0, 0, false }, "Jcc32", "!1c !0t" },
537 { kX86Jmp8, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xEB, 0, 0, 0, 0, 0, false }, "Jmp8", "!0t" },
538 { kX86Jmp32, kJmp, IS_UNARY_OP | IS_BRANCH | NEEDS_FIXUP, { 0, 0, 0xE9, 0, 0, 0, 0, 0, false }, "Jmp32", "!0t" },
539 { kX86JmpR, kJmp, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpR", "!0r" },
540 { kX86Jecxz8, kJmp, NO_OPERAND | IS_BRANCH | NEEDS_FIXUP | REG_USEC, { 0, 0, 0xE3, 0, 0, 0, 0, 0, false }, "Jecxz", "!0t" },
541 { kX86JmpT, kJmp, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 4, 0, 0, false }, "JmpT", "fs:[!0d]" },
542 { kX86CallR, kCall, IS_UNARY_OP | IS_BRANCH | REG_USE0, { 0, 0, 0xE8, 0, 0, 0, 0, 0, false }, "CallR", "!0r" },
543 { kX86CallM, kCall, IS_BINARY_OP | IS_BRANCH | IS_LOAD | REG_USE0, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallM", "[!0r+!1d]" },
544 { kX86CallA, kCall, IS_QUAD_OP | IS_BRANCH | IS_LOAD | REG_USE01, { 0, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallA", "[!0r+!1r<<!2d+!3d]" },
545 { kX86CallT, kCall, IS_UNARY_OP | IS_BRANCH | IS_LOAD, { THREAD_PREFIX, 0, 0xFF, 0, 0, 2, 0, 0, false }, "CallT", "fs:[!0d]" },
546 { kX86CallI, kCall, IS_UNARY_OP | IS_BRANCH, { 0, 0, 0xE8, 0, 0, 0, 0, 4, false }, "CallI", "!0d" },
547 { kX86Ret, kNullary, NO_OPERAND | IS_BRANCH, { 0, 0, 0xC3, 0, 0, 0, 0, 0, false }, "Ret", "" },
548
549 { kX86PcRelLoadRA, kPcRel, IS_LOAD | IS_QUIN_OP | REG_DEF0_USE12, { 0, 0, 0x8B, 0, 0, 0, 0, 0, false }, "PcRelLoadRA", "!0r,[!1r+!2r<<!3d+!4p]" },
550 { kX86PcRelAdr, kPcRel, IS_LOAD | IS_BINARY_OP | REG_DEF0, { 0, 0, 0xB8, 0, 0, 0, 0, 4, false }, "PcRelAdr", "!0r,!1p" },
551 { kX86RepneScasw, kNullary, NO_OPERAND | REG_USEA | REG_USEC | SETS_CCODES, { 0x66, 0xF2, 0xAF, 0, 0, 0, 0, 0, false }, "RepNE ScasW", "" },
552 };
553
operator <<(std::ostream & os,const X86OpCode & rhs)554 std::ostream& operator<<(std::ostream& os, const X86OpCode& rhs) {
555 os << X86Mir2Lir::EncodingMap[rhs].name;
556 return os;
557 }
558
NeedsRex(int32_t raw_reg)559 static bool NeedsRex(int32_t raw_reg) {
560 return raw_reg != kRIPReg && RegStorage::RegNum(raw_reg) > 7;
561 }
562
LowRegisterBits(int32_t raw_reg)563 static uint8_t LowRegisterBits(int32_t raw_reg) {
564 uint8_t low_reg = RegStorage::RegNum(raw_reg) & kRegNumMask32; // 3 bits
565 DCHECK_LT(low_reg, 8);
566 return low_reg;
567 }
568
HasModrm(const X86EncodingMap * entry)569 static bool HasModrm(const X86EncodingMap* entry) {
570 switch (entry->kind) {
571 case kNullary: return false;
572 case kRegOpcode: return false;
573 default: return true;
574 }
575 }
576
HasSib(const X86EncodingMap * entry)577 static bool HasSib(const X86EncodingMap* entry) {
578 switch (entry->kind) {
579 case kArray: return true;
580 case kArrayReg: return true;
581 case kRegArray: return true;
582 case kArrayImm: return true;
583 case kRegArrayImm: return true;
584 case kShiftArrayImm: return true;
585 case kShiftArrayCl: return true;
586 case kArrayCond: return true;
587 case kCall:
588 switch (entry->opcode) {
589 case kX86CallA: return true;
590 default: return false;
591 }
592 case kPcRel:
593 switch (entry->opcode) {
594 case kX86PcRelLoadRA: return true;
595 default: return false;
596 }
597 default: return false;
598 }
599 }
600
ModrmIsRegReg(const X86EncodingMap * entry)601 static bool ModrmIsRegReg(const X86EncodingMap* entry) {
602 switch (entry->kind) {
603 // There is no modrm for this kind of instruction, therefore the reg doesn't form part of the
604 // modrm:
605 case kNullary: return true;
606 case kRegOpcode: return true;
607 case kMovRegImm: return true;
608 // Regular modrm value of 3 cases, when there is one register the other register holds an
609 // opcode so the base register is special.
610 case kReg: return true;
611 case kRegReg: return true;
612 case kRegRegStore: return true;
613 case kRegImm: return true;
614 case kRegRegImm: return true;
615 case kRegRegImmStore: return true;
616 case kShiftRegImm: return true;
617 case kShiftRegCl: return true;
618 case kRegCond: return true;
619 case kRegRegCond: return true;
620 case kShiftRegRegCl: return true;
621 case kJmp:
622 switch (entry->opcode) {
623 case kX86JmpR: return true;
624 default: return false;
625 }
626 case kCall:
627 switch (entry->opcode) {
628 case kX86CallR: return true;
629 default: return false;
630 }
631 default: return false;
632 }
633 }
634
IsByteSecondOperand(const X86EncodingMap * entry)635 static bool IsByteSecondOperand(const X86EncodingMap* entry) {
636 return StartsWith(entry->name, "Movzx8") || StartsWith(entry->name, "Movsx8");
637 }
638
ComputeSize(const X86EncodingMap * entry,int32_t raw_reg,int32_t raw_index,int32_t raw_base,int32_t displacement)639 size_t X86Mir2Lir::ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index,
640 int32_t raw_base, int32_t displacement) {
641 bool has_modrm = HasModrm(entry);
642 bool has_sib = HasSib(entry);
643 bool r8_form = entry->skeleton.r8_form;
644 bool modrm_is_reg_reg = ModrmIsRegReg(entry);
645 if (has_sib) {
646 DCHECK(!modrm_is_reg_reg);
647 }
648 size_t size = 0;
649 if (entry->skeleton.prefix1 > 0) {
650 ++size;
651 if (entry->skeleton.prefix2 > 0) {
652 ++size;
653 }
654 }
655 if (cu_->target64 || kIsDebugBuild) {
656 bool registers_need_rex_prefix = NeedsRex(raw_reg) || NeedsRex(raw_index) || NeedsRex(raw_base);
657 if (r8_form) {
658 // Do we need an empty REX prefix to normalize byte registers?
659 registers_need_rex_prefix = registers_need_rex_prefix ||
660 (RegStorage::RegNum(raw_reg) >= 4 && !IsByteSecondOperand(entry));
661 registers_need_rex_prefix = registers_need_rex_prefix ||
662 (modrm_is_reg_reg && (RegStorage::RegNum(raw_base) >= 4));
663 }
664 if (registers_need_rex_prefix) {
665 DCHECK(cu_->target64) << "Attempt to use a 64-bit only addressable register "
666 << RegStorage::RegNum(raw_reg) << " with instruction " << entry->name;
667 if (entry->skeleton.prefix1 != REX_W && entry->skeleton.prefix2 != REX_W
668 && entry->skeleton.prefix1 != REX && entry->skeleton.prefix2 != REX) {
669 ++size; // rex
670 }
671 }
672 }
673 ++size; // opcode
674 if (entry->skeleton.opcode == 0x0F) {
675 ++size;
676 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {
677 ++size;
678 }
679 }
680 if (has_modrm) {
681 ++size; // modrm
682 }
683 if (!modrm_is_reg_reg) {
684 if (has_sib || (LowRegisterBits(raw_base) == rs_rX86_SP_32.GetRegNum())
685 || (cu_->target64 && entry->skeleton.prefix1 == THREAD_PREFIX)) {
686 // SP requires a SIB byte.
687 // GS access also needs a SIB byte for absolute adressing in 64-bit mode.
688 ++size;
689 }
690 if (displacement != 0 || LowRegisterBits(raw_base) == rs_rBP.GetRegNum()) {
691 // BP requires an explicit displacement, even when it's 0.
692 if (entry->opcode != kX86Lea32RA && entry->opcode != kX86Lea64RA &&
693 entry->opcode != kX86Lea32RM && entry->opcode != kX86Lea64RM) {
694 DCHECK_NE(entry->flags & (IS_LOAD | IS_STORE), UINT64_C(0)) << entry->name;
695 }
696 if (raw_base == kRIPReg) {
697 DCHECK(cu_->target64) <<
698 "Attempt to use a 64-bit RIP adressing with instruction " << entry->name;
699 size += 4;
700 } else {
701 size += IS_SIMM8(displacement) ? 1 : 4;
702 }
703 }
704 }
705 size += entry->skeleton.immediate_bytes;
706 return size;
707 }
708
GetInsnSize(LIR * lir)709 size_t X86Mir2Lir::GetInsnSize(LIR* lir) {
710 DCHECK(!IsPseudoLirOp(lir->opcode));
711 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];
712 DCHECK_EQ(entry->opcode, lir->opcode) << entry->name;
713
714 switch (entry->kind) {
715 case kData:
716 return 4; // 4 bytes of data.
717 case kNop:
718 return lir->operands[0]; // Length of nop is sole operand.
719 case kNullary:
720 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0);
721 case kRegOpcode: // lir operands - 0: reg
722 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0);
723 case kReg: // lir operands - 0: reg
724 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0);
725 case kMem: // lir operands - 0: base, 1: disp
726 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]);
727 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp
728 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]);
729 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg
730 return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]);
731 case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate
732 return ComputeSize(entry, lir->operands[2], NO_REG, lir->operands[0], lir->operands[1]);
733 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
734 return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0],
735 lir->operands[3]);
736 case kThreadReg: // lir operands - 0: disp, 1: reg
737 // Thread displacement size is always 32bit.
738 return ComputeSize(entry, lir->operands[1], NO_REG, NO_REG, 0x12345678);
739 case kRegReg: // lir operands - 0: reg1, 1: reg2
740 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0);
741 case kRegRegStore: // lir operands - 0: reg2, 1: reg1
742 return ComputeSize(entry, lir->operands[1], NO_REG, lir->operands[0], 0);
743 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp
744 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]);
745 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp
746 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1],
747 lir->operands[4]);
748 case kRegThread: // lir operands - 0: reg, 1: disp
749 // Thread displacement size is always 32bit.
750 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0x12345678);
751 case kRegImm: { // lir operands - 0: reg, 1: immediate
752 size_t size = ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0);
753 // AX opcodes don't require the modrm byte.
754 if (entry->skeleton.ax_opcode == 0) {
755 return size;
756 } else {
757 return size - (RegStorage::RegNum(lir->operands[0]) == rs_rAX.GetRegNum() ? 1 : 0);
758 }
759 }
760 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate
761 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]);
762 case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate
763 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]);
764 case kThreadImm: // lir operands - 0: disp, 1: imm
765 // Thread displacement size is always 32bit.
766 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678);
767 case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm
768 // Note: RegRegImm form passes reg2 as index but encodes it using base.
769 return ComputeSize(entry, lir->operands[0], lir->operands[1], NO_REG, 0);
770 case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm
771 // Note: RegRegImmStore form passes reg1 as index but encodes it using base.
772 return ComputeSize(entry, lir->operands[1], lir->operands[0], NO_REG, 0);
773 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm
774 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]);
775 case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm
776 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1],
777 lir->operands[4]);
778 case kMovRegImm: // lir operands - 0: reg, 1: immediate
779 case kMovRegQuadImm:
780 return ((entry->skeleton.prefix1 != 0 || NeedsRex(lir->operands[0])) ? 1 : 0) + 1 +
781 entry->skeleton.immediate_bytes;
782 case kShiftRegImm: // lir operands - 0: reg, 1: immediate
783 // Shift by immediate one has a shorter opcode.
784 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0) -
785 (lir->operands[1] == 1 ? 1 : 0);
786 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate
787 // Shift by immediate one has a shorter opcode.
788 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]) -
789 (lir->operands[2] == 1 ? 1 : 0);
790 case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate
791 // Shift by immediate one has a shorter opcode.
792 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]) -
793 (lir->operands[4] == 1 ? 1 : 0);
794 case kShiftRegCl: // lir operands - 0: reg, 1: cl
795 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[1]));
796 // Note: ShiftRegCl form passes reg as reg but encodes it using base.
797 return ComputeSize(entry, lir->operands[0], NO_REG, NO_REG, 0);
798 case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl
799 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[2]));
800 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]);
801 case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cl
802 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[4]));
803 return ComputeSize(entry, lir->operands[4], lir->operands[1], lir->operands[0],
804 lir->operands[3]);
805 case kShiftRegRegCl: // lir operands - 0: reg1, 1: reg2, 2: cl
806 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(lir->operands[2]));
807 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0);
808 case kRegCond: // lir operands - 0: reg, 1: cond
809 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], 0);
810 case kMemCond: // lir operands - 0: base, 1: disp, 2: cond
811 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]);
812 case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond
813 DCHECK_EQ(false, entry->skeleton.r8_form);
814 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]);
815 case kRegRegCond: // lir operands - 0: reg1, 1: reg2, 2: cond
816 DCHECK_EQ(false, entry->skeleton.r8_form);
817 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], 0);
818 case kRegMemCond: // lir operands - 0: reg, 1: base, 2: disp, 3:cond
819 DCHECK_EQ(false, entry->skeleton.r8_form);
820 return ComputeSize(entry, lir->operands[0], NO_REG, lir->operands[1], lir->operands[2]);
821 case kJcc:
822 if (lir->opcode == kX86Jcc8) {
823 return 2; // opcode + rel8
824 } else {
825 DCHECK(lir->opcode == kX86Jcc32);
826 return 6; // 2 byte opcode + rel32
827 }
828 case kJmp:
829 if (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jecxz8) {
830 return 2; // opcode + rel8
831 } else if (lir->opcode == kX86Jmp32) {
832 return 5; // opcode + rel32
833 } else if (lir->opcode == kX86JmpT) {
834 // Thread displacement size is always 32bit.
835 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678);
836 } else {
837 DCHECK(lir->opcode == kX86JmpR);
838 if (NeedsRex(lir->operands[0])) {
839 return 3; // REX.B + opcode + modrm
840 } else {
841 return 2; // opcode + modrm
842 }
843 }
844 case kCall:
845 switch (lir->opcode) {
846 case kX86CallI: return 5; // opcode 0:disp
847 case kX86CallR: return 2; // opcode modrm
848 case kX86CallM: // lir operands - 0: base, 1: disp
849 return ComputeSize(entry, NO_REG, NO_REG, lir->operands[0], lir->operands[1]);
850 case kX86CallA: // lir operands - 0: base, 1: index, 2: scale, 3: disp
851 return ComputeSize(entry, NO_REG, lir->operands[1], lir->operands[0], lir->operands[3]);
852 case kX86CallT: // lir operands - 0: disp
853 // Thread displacement size is always 32bit.
854 return ComputeSize(entry, NO_REG, NO_REG, NO_REG, 0x12345678);
855 default:
856 break;
857 }
858 break;
859 case kPcRel:
860 if (entry->opcode == kX86PcRelLoadRA) {
861 // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table
862 // Force the displacement size to 32bit, it will hold a computed offset later.
863 return ComputeSize(entry, lir->operands[0], lir->operands[2], lir->operands[1],
864 0x12345678);
865 } else {
866 DCHECK_EQ(entry->opcode, kX86PcRelAdr);
867 return 5; // opcode with reg + 4 byte immediate
868 }
869 case kUnimplemented:
870 break;
871 }
872 UNIMPLEMENTED(FATAL) << "Unimplemented size encoding for: " << entry->name;
873 return 0;
874 }
875
ModrmForDisp(int base,int disp)876 static uint8_t ModrmForDisp(int base, int disp) {
877 // BP requires an explicit disp, so do not omit it in the 0 case
878 if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) {
879 return 0;
880 } else if (IS_SIMM8(disp)) {
881 return 1;
882 } else {
883 return 2;
884 }
885 }
886
CheckValidByteRegister(const X86EncodingMap * entry,int32_t raw_reg)887 void X86Mir2Lir::CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg) {
888 if (kIsDebugBuild) {
889 // Sanity check r8_form is correctly specified.
890 if (entry->skeleton.r8_form) {
891 CHECK(strchr(entry->name, '8') != nullptr) << entry->name;
892 } else {
893 if (entry->skeleton.immediate_bytes != 1) { // Ignore ...I8 instructions.
894 if (!StartsWith(entry->name, "Movzx8") && !StartsWith(entry->name, "Movsx8")
895 && !StartsWith(entry->name, "Movzx8q") && !StartsWith(entry->name, "Movsx8q")) {
896 CHECK(strchr(entry->name, '8') == nullptr) << entry->name;
897 }
898 }
899 }
900 if (RegStorage::RegNum(raw_reg) >= 4) {
901 // ah, bh, ch and dh are not valid registers in 32-bit.
902 CHECK(cu_->target64 || !entry->skeleton.r8_form)
903 << "Invalid register " << static_cast<int>(RegStorage::RegNum(raw_reg))
904 << " for instruction " << entry->name << " in "
905 << PrettyMethod(cu_->method_idx, *cu_->dex_file);
906 }
907 }
908 }
909
EmitPrefix(const X86EncodingMap * entry,int32_t raw_reg_r,int32_t raw_reg_x,int32_t raw_reg_b)910 void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry,
911 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b) {
912 // REX.WRXB
913 // W - 64-bit operand
914 // R - MODRM.reg
915 // X - SIB.index
916 // B - MODRM.rm/SIB.base
917 bool w = (entry->skeleton.prefix1 == REX_W) || (entry->skeleton.prefix2 == REX_W);
918 bool r = NeedsRex(raw_reg_r);
919 bool x = NeedsRex(raw_reg_x);
920 bool b = NeedsRex(raw_reg_b);
921 bool r8_form = entry->skeleton.r8_form;
922 bool modrm_is_reg_reg = ModrmIsRegReg(entry);
923
924 uint8_t rex = 0;
925 if (r8_form) {
926 // Do we need an empty REX prefix to normalize byte register addressing?
927 if (RegStorage::RegNum(raw_reg_r) >= 4 && !IsByteSecondOperand(entry)) {
928 rex |= REX; // REX.0000
929 } else if (modrm_is_reg_reg && RegStorage::RegNum(raw_reg_b) >= 4) {
930 rex |= REX; // REX.0000
931 }
932 }
933 if (w) {
934 rex |= REX_W; // REX.W000
935 }
936 if (r) {
937 rex |= REX_R; // REX.0R00
938 }
939 if (x) {
940 rex |= REX_X; // REX.00X0
941 }
942 if (b) {
943 rex |= REX_B; // REX.000B
944 }
945 if (entry->skeleton.prefix1 != 0) {
946 if (cu_->target64 && entry->skeleton.prefix1 == THREAD_PREFIX) {
947 // 64 bit addresses by GS, not FS.
948 code_buffer_.push_back(THREAD_PREFIX_GS);
949 } else {
950 if (entry->skeleton.prefix1 == REX_W || entry->skeleton.prefix1 == REX) {
951 DCHECK(cu_->target64);
952 rex |= entry->skeleton.prefix1;
953 code_buffer_.push_back(rex);
954 rex = 0;
955 } else {
956 code_buffer_.push_back(entry->skeleton.prefix1);
957 }
958 }
959 if (entry->skeleton.prefix2 != 0) {
960 if (entry->skeleton.prefix2 == REX_W || entry->skeleton.prefix1 == REX) {
961 DCHECK(cu_->target64);
962 rex |= entry->skeleton.prefix2;
963 code_buffer_.push_back(rex);
964 rex = 0;
965 } else {
966 code_buffer_.push_back(entry->skeleton.prefix2);
967 }
968 }
969 } else {
970 DCHECK_EQ(0, entry->skeleton.prefix2);
971 }
972 if (rex != 0) {
973 DCHECK(cu_->target64);
974 code_buffer_.push_back(rex);
975 }
976 }
977
EmitOpcode(const X86EncodingMap * entry)978 void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) {
979 code_buffer_.push_back(entry->skeleton.opcode);
980 if (entry->skeleton.opcode == 0x0F) {
981 code_buffer_.push_back(entry->skeleton.extra_opcode1);
982 if (entry->skeleton.extra_opcode1 == 0x38 || entry->skeleton.extra_opcode1 == 0x3A) {
983 code_buffer_.push_back(entry->skeleton.extra_opcode2);
984 } else {
985 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
986 }
987 } else {
988 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
989 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
990 }
991 }
992
EmitPrefixAndOpcode(const X86EncodingMap * entry,int32_t raw_reg_r,int32_t raw_reg_x,int32_t raw_reg_b)993 void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry,
994 int32_t raw_reg_r, int32_t raw_reg_x, int32_t raw_reg_b) {
995 EmitPrefix(entry, raw_reg_r, raw_reg_x, raw_reg_b);
996 EmitOpcode(entry);
997 }
998
EmitDisp(uint8_t base,int32_t disp)999 void X86Mir2Lir::EmitDisp(uint8_t base, int32_t disp) {
1000 // BP requires an explicit disp, so do not omit it in the 0 case
1001 if (disp == 0 && RegStorage::RegNum(base) != rs_rBP.GetRegNum()) {
1002 return;
1003 } else if (IS_SIMM8(disp)) {
1004 code_buffer_.push_back(disp & 0xFF);
1005 } else {
1006 code_buffer_.push_back(disp & 0xFF);
1007 code_buffer_.push_back((disp >> 8) & 0xFF);
1008 code_buffer_.push_back((disp >> 16) & 0xFF);
1009 code_buffer_.push_back((disp >> 24) & 0xFF);
1010 }
1011 }
1012
EmitModrmThread(uint8_t reg_or_opcode)1013 void X86Mir2Lir::EmitModrmThread(uint8_t reg_or_opcode) {
1014 if (cu_->target64) {
1015 // Absolute adressing for GS access.
1016 uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rX86_SP_32.GetRegNum();
1017 code_buffer_.push_back(modrm);
1018 uint8_t sib = (0/*TIMES_1*/ << 6) | (rs_rX86_SP_32.GetRegNum() << 3) | rs_rBP.GetRegNum();
1019 code_buffer_.push_back(sib);
1020 } else {
1021 uint8_t modrm = (0 << 6) | (reg_or_opcode << 3) | rs_rBP.GetRegNum();
1022 code_buffer_.push_back(modrm);
1023 }
1024 }
1025
EmitModrmDisp(uint8_t reg_or_opcode,uint8_t base,int32_t disp)1026 void X86Mir2Lir::EmitModrmDisp(uint8_t reg_or_opcode, uint8_t base, int32_t disp) {
1027 DCHECK_LT(reg_or_opcode, 8);
1028 if (base == kRIPReg) {
1029 // x86_64 RIP handling: always 32 bit displacement.
1030 uint8_t modrm = (0x0 << 6) | (reg_or_opcode << 3) | 0x5;
1031 code_buffer_.push_back(modrm);
1032 code_buffer_.push_back(disp & 0xFF);
1033 code_buffer_.push_back((disp >> 8) & 0xFF);
1034 code_buffer_.push_back((disp >> 16) & 0xFF);
1035 code_buffer_.push_back((disp >> 24) & 0xFF);
1036 } else {
1037 DCHECK_LT(base, 8);
1038 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | (reg_or_opcode << 3) | base;
1039 code_buffer_.push_back(modrm);
1040 if (base == rs_rX86_SP_32.GetRegNum()) {
1041 // Special SIB for SP base
1042 code_buffer_.push_back(0 << 6 | rs_rX86_SP_32.GetRegNum() << 3 | rs_rX86_SP_32.GetRegNum());
1043 }
1044 EmitDisp(base, disp);
1045 }
1046 }
1047
EmitModrmSibDisp(uint8_t reg_or_opcode,uint8_t base,uint8_t index,int scale,int32_t disp)1048 void X86Mir2Lir::EmitModrmSibDisp(uint8_t reg_or_opcode, uint8_t base, uint8_t index,
1049 int scale, int32_t disp) {
1050 DCHECK_LT(RegStorage::RegNum(reg_or_opcode), 8);
1051 uint8_t modrm = (ModrmForDisp(base, disp) << 6) | RegStorage::RegNum(reg_or_opcode) << 3 |
1052 rs_rX86_SP_32.GetRegNum();
1053 code_buffer_.push_back(modrm);
1054 DCHECK_LT(scale, 4);
1055 DCHECK_LT(RegStorage::RegNum(index), 8);
1056 DCHECK_LT(RegStorage::RegNum(base), 8);
1057 uint8_t sib = (scale << 6) | (RegStorage::RegNum(index) << 3) | RegStorage::RegNum(base);
1058 code_buffer_.push_back(sib);
1059 EmitDisp(base, disp);
1060 }
1061
EmitImm(const X86EncodingMap * entry,int64_t imm)1062 void X86Mir2Lir::EmitImm(const X86EncodingMap* entry, int64_t imm) {
1063 switch (entry->skeleton.immediate_bytes) {
1064 case 1:
1065 DCHECK(IS_SIMM8(imm));
1066 code_buffer_.push_back(imm & 0xFF);
1067 break;
1068 case 2:
1069 DCHECK(IS_SIMM16(imm));
1070 code_buffer_.push_back(imm & 0xFF);
1071 code_buffer_.push_back((imm >> 8) & 0xFF);
1072 break;
1073 case 4:
1074 DCHECK(IS_SIMM32(imm));
1075 code_buffer_.push_back(imm & 0xFF);
1076 code_buffer_.push_back((imm >> 8) & 0xFF);
1077 code_buffer_.push_back((imm >> 16) & 0xFF);
1078 code_buffer_.push_back((imm >> 24) & 0xFF);
1079 break;
1080 case 8:
1081 code_buffer_.push_back(imm & 0xFF);
1082 code_buffer_.push_back((imm >> 8) & 0xFF);
1083 code_buffer_.push_back((imm >> 16) & 0xFF);
1084 code_buffer_.push_back((imm >> 24) & 0xFF);
1085 code_buffer_.push_back((imm >> 32) & 0xFF);
1086 code_buffer_.push_back((imm >> 40) & 0xFF);
1087 code_buffer_.push_back((imm >> 48) & 0xFF);
1088 code_buffer_.push_back((imm >> 56) & 0xFF);
1089 break;
1090 default:
1091 LOG(FATAL) << "Unexpected immediate bytes (" << entry->skeleton.immediate_bytes
1092 << ") for instruction: " << entry->name;
1093 break;
1094 }
1095 }
1096
EmitNullary(const X86EncodingMap * entry)1097 void X86Mir2Lir::EmitNullary(const X86EncodingMap* entry) {
1098 DCHECK_EQ(false, entry->skeleton.r8_form);
1099 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG);
1100 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1101 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1102 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1103 }
1104
EmitOpRegOpcode(const X86EncodingMap * entry,int32_t raw_reg)1105 void X86Mir2Lir::EmitOpRegOpcode(const X86EncodingMap* entry, int32_t raw_reg) {
1106 DCHECK_EQ(false, entry->skeleton.r8_form);
1107 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg);
1108 // There's no 3-byte instruction with +rd
1109 DCHECK(entry->skeleton.opcode != 0x0F ||
1110 (entry->skeleton.extra_opcode1 != 0x38 && entry->skeleton.extra_opcode1 != 0x3A));
1111 DCHECK(!RegStorage::IsFloat(raw_reg));
1112 uint8_t low_reg = LowRegisterBits(raw_reg);
1113 code_buffer_.back() += low_reg;
1114 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1115 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1116 }
1117
EmitOpReg(const X86EncodingMap * entry,int32_t raw_reg)1118 void X86Mir2Lir::EmitOpReg(const X86EncodingMap* entry, int32_t raw_reg) {
1119 CheckValidByteRegister(entry, raw_reg);
1120 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_reg);
1121 uint8_t low_reg = LowRegisterBits(raw_reg);
1122 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg;
1123 code_buffer_.push_back(modrm);
1124 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1125 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1126 }
1127
EmitOpMem(const X86EncodingMap * entry,int32_t raw_base,int32_t disp)1128 void X86Mir2Lir::EmitOpMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) {
1129 DCHECK_EQ(false, entry->skeleton.r8_form);
1130 EmitPrefix(entry, NO_REG, NO_REG, raw_base);
1131 code_buffer_.push_back(entry->skeleton.opcode);
1132 DCHECK_NE(0x0F, entry->skeleton.opcode);
1133 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1134 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1135 uint8_t low_base = LowRegisterBits(raw_base);
1136 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp);
1137 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1138 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1139 }
1140
EmitOpArray(const X86EncodingMap * entry,int32_t raw_base,int32_t raw_index,int scale,int32_t disp)1141 void X86Mir2Lir::EmitOpArray(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index,
1142 int scale, int32_t disp) {
1143 DCHECK_EQ(false, entry->skeleton.r8_form);
1144 EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base);
1145 uint8_t low_index = LowRegisterBits(raw_index);
1146 uint8_t low_base = LowRegisterBits(raw_base);
1147 EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp);
1148 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1149 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1150 }
1151
EmitMemReg(const X86EncodingMap * entry,int32_t raw_base,int32_t disp,int32_t raw_reg)1152 void X86Mir2Lir::EmitMemReg(const X86EncodingMap* entry, int32_t raw_base, int32_t disp,
1153 int32_t raw_reg) {
1154 CheckValidByteRegister(entry, raw_reg);
1155 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base);
1156 uint8_t low_reg = LowRegisterBits(raw_reg);
1157 uint8_t low_base = (raw_base == kRIPReg) ? raw_base : LowRegisterBits(raw_base);
1158 EmitModrmDisp(low_reg, low_base, disp);
1159 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1160 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1161 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1162 }
1163
EmitRegMem(const X86EncodingMap * entry,int32_t raw_reg,int32_t raw_base,int32_t disp)1164 void X86Mir2Lir::EmitRegMem(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base,
1165 int32_t disp) {
1166 // Opcode will flip operands.
1167 EmitMemReg(entry, raw_base, disp, raw_reg);
1168 }
1169
EmitRegArray(const X86EncodingMap * entry,int32_t raw_reg,int32_t raw_base,int32_t raw_index,int scale,int32_t disp)1170 void X86Mir2Lir::EmitRegArray(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base,
1171 int32_t raw_index, int scale, int32_t disp) {
1172 CheckValidByteRegister(entry, raw_reg);
1173 EmitPrefixAndOpcode(entry, raw_reg, raw_index, raw_base);
1174 uint8_t low_reg = LowRegisterBits(raw_reg);
1175 uint8_t low_index = LowRegisterBits(raw_index);
1176 uint8_t low_base = LowRegisterBits(raw_base);
1177 EmitModrmSibDisp(low_reg, low_base, low_index, scale, disp);
1178 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1179 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1180 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1181 }
1182
EmitArrayReg(const X86EncodingMap * entry,int32_t raw_base,int32_t raw_index,int scale,int32_t disp,int32_t raw_reg)1183 void X86Mir2Lir::EmitArrayReg(const X86EncodingMap* entry, int32_t raw_base, int32_t raw_index,
1184 int scale, int32_t disp, int32_t raw_reg) {
1185 // Opcode will flip operands.
1186 EmitRegArray(entry, raw_reg, raw_base, raw_index, scale, disp);
1187 }
1188
EmitMemImm(const X86EncodingMap * entry,int32_t raw_base,int32_t disp,int32_t imm)1189 void X86Mir2Lir::EmitMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp,
1190 int32_t imm) {
1191 DCHECK_EQ(false, entry->skeleton.r8_form);
1192 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base);
1193 uint8_t low_base = LowRegisterBits(raw_base);
1194 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp);
1195 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1196 EmitImm(entry, imm);
1197 }
1198
EmitArrayImm(const X86EncodingMap * entry,int32_t raw_base,int32_t raw_index,int scale,int32_t disp,int32_t imm)1199 void X86Mir2Lir::EmitArrayImm(const X86EncodingMap* entry,
1200 int32_t raw_base, int32_t raw_index, int scale, int32_t disp,
1201 int32_t imm) {
1202 DCHECK_EQ(false, entry->skeleton.r8_form);
1203 EmitPrefixAndOpcode(entry, NO_REG, raw_index, raw_base);
1204 uint8_t low_index = LowRegisterBits(raw_index);
1205 uint8_t low_base = LowRegisterBits(raw_base);
1206 EmitModrmSibDisp(entry->skeleton.modrm_opcode, low_base, low_index, scale, disp);
1207 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1208 EmitImm(entry, imm);
1209 }
1210
EmitRegThread(const X86EncodingMap * entry,int32_t raw_reg,int32_t disp)1211 void X86Mir2Lir::EmitRegThread(const X86EncodingMap* entry, int32_t raw_reg, int32_t disp) {
1212 DCHECK_EQ(false, entry->skeleton.r8_form);
1213 DCHECK_NE(entry->skeleton.prefix1, 0);
1214 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, NO_REG);
1215 uint8_t low_reg = LowRegisterBits(raw_reg);
1216 EmitModrmThread(low_reg);
1217 code_buffer_.push_back(disp & 0xFF);
1218 code_buffer_.push_back((disp >> 8) & 0xFF);
1219 code_buffer_.push_back((disp >> 16) & 0xFF);
1220 code_buffer_.push_back((disp >> 24) & 0xFF);
1221 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1222 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1223 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1224 }
1225
EmitRegReg(const X86EncodingMap * entry,int32_t raw_reg1,int32_t raw_reg2)1226 void X86Mir2Lir::EmitRegReg(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2) {
1227 if (!IsByteSecondOperand(entry)) {
1228 CheckValidByteRegister(entry, raw_reg1);
1229 }
1230 CheckValidByteRegister(entry, raw_reg2);
1231 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2);
1232 uint8_t low_reg1 = LowRegisterBits(raw_reg1);
1233 uint8_t low_reg2 = LowRegisterBits(raw_reg2);
1234 uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2;
1235 code_buffer_.push_back(modrm);
1236 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1237 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1238 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1239 }
1240
EmitRegRegImm(const X86EncodingMap * entry,int32_t raw_reg1,int32_t raw_reg2,int32_t imm)1241 void X86Mir2Lir::EmitRegRegImm(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2,
1242 int32_t imm) {
1243 DCHECK_EQ(false, entry->skeleton.r8_form);
1244 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2);
1245 uint8_t low_reg1 = LowRegisterBits(raw_reg1);
1246 uint8_t low_reg2 = LowRegisterBits(raw_reg2);
1247 uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2;
1248 code_buffer_.push_back(modrm);
1249 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1250 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1251 EmitImm(entry, imm);
1252 }
1253
EmitRegMemImm(const X86EncodingMap * entry,int32_t raw_reg,int32_t raw_base,int disp,int32_t imm)1254 void X86Mir2Lir::EmitRegMemImm(const X86EncodingMap* entry,
1255 int32_t raw_reg, int32_t raw_base, int disp, int32_t imm) {
1256 DCHECK(!RegStorage::IsFloat(raw_reg));
1257 CheckValidByteRegister(entry, raw_reg);
1258 EmitPrefixAndOpcode(entry, raw_reg, NO_REG, raw_base);
1259 uint8_t low_reg = LowRegisterBits(raw_reg);
1260 uint8_t low_base = LowRegisterBits(raw_base);
1261 EmitModrmDisp(low_reg, low_base, disp);
1262 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1263 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1264 EmitImm(entry, imm);
1265 }
1266
EmitMemRegImm(const X86EncodingMap * entry,int32_t raw_base,int32_t disp,int32_t raw_reg,int32_t imm)1267 void X86Mir2Lir::EmitMemRegImm(const X86EncodingMap* entry,
1268 int32_t raw_base, int32_t disp, int32_t raw_reg, int32_t imm) {
1269 // Opcode will flip operands.
1270 EmitRegMemImm(entry, raw_reg, raw_base, disp, imm);
1271 }
1272
EmitRegImm(const X86EncodingMap * entry,int32_t raw_reg,int32_t imm)1273 void X86Mir2Lir::EmitRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) {
1274 CheckValidByteRegister(entry, raw_reg);
1275 EmitPrefix(entry, NO_REG, NO_REG, raw_reg);
1276 if (RegStorage::RegNum(raw_reg) == rs_rAX.GetRegNum() && entry->skeleton.ax_opcode != 0) {
1277 code_buffer_.push_back(entry->skeleton.ax_opcode);
1278 } else {
1279 uint8_t low_reg = LowRegisterBits(raw_reg);
1280 EmitOpcode(entry);
1281 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg;
1282 code_buffer_.push_back(modrm);
1283 }
1284 EmitImm(entry, imm);
1285 }
1286
EmitThreadImm(const X86EncodingMap * entry,int32_t disp,int32_t imm)1287 void X86Mir2Lir::EmitThreadImm(const X86EncodingMap* entry, int32_t disp, int32_t imm) {
1288 DCHECK_EQ(false, entry->skeleton.r8_form);
1289 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG);
1290 EmitModrmThread(entry->skeleton.modrm_opcode);
1291 code_buffer_.push_back(disp & 0xFF);
1292 code_buffer_.push_back((disp >> 8) & 0xFF);
1293 code_buffer_.push_back((disp >> 16) & 0xFF);
1294 code_buffer_.push_back((disp >> 24) & 0xFF);
1295 EmitImm(entry, imm);
1296 DCHECK_EQ(entry->skeleton.ax_opcode, 0);
1297 }
1298
EmitMovRegImm(const X86EncodingMap * entry,int32_t raw_reg,int64_t imm)1299 void X86Mir2Lir::EmitMovRegImm(const X86EncodingMap* entry, int32_t raw_reg, int64_t imm) {
1300 DCHECK_EQ(false, entry->skeleton.r8_form);
1301 EmitPrefix(entry, NO_REG, NO_REG, raw_reg);
1302 uint8_t low_reg = LowRegisterBits(raw_reg);
1303 code_buffer_.push_back(0xB8 + low_reg);
1304 switch (entry->skeleton.immediate_bytes) {
1305 case 4:
1306 code_buffer_.push_back(imm & 0xFF);
1307 code_buffer_.push_back((imm >> 8) & 0xFF);
1308 code_buffer_.push_back((imm >> 16) & 0xFF);
1309 code_buffer_.push_back((imm >> 24) & 0xFF);
1310 break;
1311 case 8:
1312 code_buffer_.push_back(imm & 0xFF);
1313 code_buffer_.push_back((imm >> 8) & 0xFF);
1314 code_buffer_.push_back((imm >> 16) & 0xFF);
1315 code_buffer_.push_back((imm >> 24) & 0xFF);
1316 code_buffer_.push_back((imm >> 32) & 0xFF);
1317 code_buffer_.push_back((imm >> 40) & 0xFF);
1318 code_buffer_.push_back((imm >> 48) & 0xFF);
1319 code_buffer_.push_back((imm >> 56) & 0xFF);
1320 break;
1321 default:
1322 LOG(FATAL) << "Unsupported immediate size for EmitMovRegImm: "
1323 << static_cast<uint32_t>(entry->skeleton.immediate_bytes);
1324 }
1325 }
1326
EmitShiftRegImm(const X86EncodingMap * entry,int32_t raw_reg,int32_t imm)1327 void X86Mir2Lir::EmitShiftRegImm(const X86EncodingMap* entry, int32_t raw_reg, int32_t imm) {
1328 CheckValidByteRegister(entry, raw_reg);
1329 EmitPrefix(entry, NO_REG, NO_REG, raw_reg);
1330 if (imm != 1) {
1331 code_buffer_.push_back(entry->skeleton.opcode);
1332 } else {
1333 // Shorter encoding for 1 bit shift
1334 code_buffer_.push_back(entry->skeleton.ax_opcode);
1335 }
1336 DCHECK_NE(0x0F, entry->skeleton.opcode);
1337 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1338 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1339 uint8_t low_reg = LowRegisterBits(raw_reg);
1340 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg;
1341 code_buffer_.push_back(modrm);
1342 if (imm != 1) {
1343 DCHECK_EQ(entry->skeleton.immediate_bytes, 1);
1344 DCHECK(IS_SIMM8(imm));
1345 code_buffer_.push_back(imm & 0xFF);
1346 }
1347 }
1348
EmitShiftRegCl(const X86EncodingMap * entry,int32_t raw_reg,int32_t raw_cl)1349 void X86Mir2Lir::EmitShiftRegCl(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_cl) {
1350 CheckValidByteRegister(entry, raw_reg);
1351 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl));
1352 EmitPrefix(entry, NO_REG, NO_REG, raw_reg);
1353 code_buffer_.push_back(entry->skeleton.opcode);
1354 DCHECK_NE(0x0F, entry->skeleton.opcode);
1355 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1356 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1357 uint8_t low_reg = LowRegisterBits(raw_reg);
1358 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg;
1359 code_buffer_.push_back(modrm);
1360 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1361 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1362 }
1363
EmitShiftMemCl(const X86EncodingMap * entry,int32_t raw_base,int32_t displacement,int32_t raw_cl)1364 void X86Mir2Lir::EmitShiftMemCl(const X86EncodingMap* entry, int32_t raw_base,
1365 int32_t displacement, int32_t raw_cl) {
1366 DCHECK_EQ(false, entry->skeleton.r8_form);
1367 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl));
1368 EmitPrefix(entry, NO_REG, NO_REG, raw_base);
1369 code_buffer_.push_back(entry->skeleton.opcode);
1370 DCHECK_NE(0x0F, entry->skeleton.opcode);
1371 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1372 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1373 uint8_t low_base = LowRegisterBits(raw_base);
1374 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, displacement);
1375 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1376 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1377 }
1378
EmitShiftRegRegCl(const X86EncodingMap * entry,int32_t raw_reg1,int32_t raw_reg2,int32_t raw_cl)1379 void X86Mir2Lir::EmitShiftRegRegCl(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2, int32_t raw_cl) {
1380 DCHECK_EQ(false, entry->skeleton.r8_form);
1381 DCHECK_EQ(rs_rCX.GetRegNum(), RegStorage::RegNum(raw_cl));
1382 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2);
1383 uint8_t low_reg1 = LowRegisterBits(raw_reg1);
1384 uint8_t low_reg2 = LowRegisterBits(raw_reg2);
1385 uint8_t modrm = (3 << 6) | (low_reg1 << 3) | low_reg2;
1386 code_buffer_.push_back(modrm);
1387 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1388 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1389 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1390 }
1391
EmitShiftMemImm(const X86EncodingMap * entry,int32_t raw_base,int32_t disp,int32_t imm)1392 void X86Mir2Lir::EmitShiftMemImm(const X86EncodingMap* entry, int32_t raw_base, int32_t disp,
1393 int32_t imm) {
1394 DCHECK_EQ(false, entry->skeleton.r8_form);
1395 EmitPrefix(entry, NO_REG, NO_REG, raw_base);
1396 if (imm != 1) {
1397 code_buffer_.push_back(entry->skeleton.opcode);
1398 } else {
1399 // Shorter encoding for 1 bit shift
1400 code_buffer_.push_back(entry->skeleton.ax_opcode);
1401 }
1402 DCHECK_NE(0x0F, entry->skeleton.opcode);
1403 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1404 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1405 uint8_t low_base = LowRegisterBits(raw_base);
1406 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp);
1407 if (imm != 1) {
1408 DCHECK_EQ(entry->skeleton.immediate_bytes, 1);
1409 DCHECK(IS_SIMM8(imm));
1410 code_buffer_.push_back(imm & 0xFF);
1411 }
1412 }
1413
EmitRegCond(const X86EncodingMap * entry,int32_t raw_reg,int32_t cc)1414 void X86Mir2Lir::EmitRegCond(const X86EncodingMap* entry, int32_t raw_reg, int32_t cc) {
1415 CheckValidByteRegister(entry, raw_reg);
1416 EmitPrefix(entry, NO_REG, NO_REG, raw_reg);
1417 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1418 DCHECK_EQ(0x0F, entry->skeleton.opcode);
1419 code_buffer_.push_back(0x0F);
1420 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);
1421 DCHECK_GE(cc, 0);
1422 DCHECK_LT(cc, 16);
1423 code_buffer_.push_back(0x90 | cc);
1424 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1425 uint8_t low_reg = LowRegisterBits(raw_reg);
1426 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg;
1427 code_buffer_.push_back(modrm);
1428 DCHECK_EQ(entry->skeleton.immediate_bytes, 0);
1429 }
1430
EmitMemCond(const X86EncodingMap * entry,int32_t raw_base,int32_t disp,int32_t cc)1431 void X86Mir2Lir::EmitMemCond(const X86EncodingMap* entry, int32_t raw_base, int32_t disp,
1432 int32_t cc) {
1433 DCHECK_EQ(false, entry->skeleton.r8_form);
1434 if (entry->skeleton.prefix1 != 0) {
1435 code_buffer_.push_back(entry->skeleton.prefix1);
1436 if (entry->skeleton.prefix2 != 0) {
1437 code_buffer_.push_back(entry->skeleton.prefix2);
1438 }
1439 } else {
1440 DCHECK_EQ(0, entry->skeleton.prefix2);
1441 }
1442 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1443 DCHECK_EQ(0x0F, entry->skeleton.opcode);
1444 code_buffer_.push_back(0x0F);
1445 DCHECK_EQ(0x90, entry->skeleton.extra_opcode1);
1446 DCHECK_GE(cc, 0);
1447 DCHECK_LT(cc, 16);
1448 code_buffer_.push_back(0x90 | cc);
1449 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1450 uint8_t low_base = LowRegisterBits(raw_base);
1451 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp);
1452 DCHECK_EQ(entry->skeleton.immediate_bytes, 0);
1453 }
1454
EmitRegRegCond(const X86EncodingMap * entry,int32_t raw_reg1,int32_t raw_reg2,int32_t cc)1455 void X86Mir2Lir::EmitRegRegCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_reg2,
1456 int32_t cc) {
1457 // Generate prefix and opcode without the condition.
1458 DCHECK_EQ(false, entry->skeleton.r8_form);
1459 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_reg2);
1460
1461 // Now add the condition. The last byte of opcode is the one that receives it.
1462 DCHECK_GE(cc, 0);
1463 DCHECK_LT(cc, 16);
1464 code_buffer_.back() += cc;
1465
1466 // Not expecting to have to encode immediate or do anything special for ModR/M since there are
1467 // two registers.
1468 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1469 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1470
1471 // For register to register encoding, the mod is 3.
1472 const uint8_t mod = (3 << 6);
1473
1474 // Encode the ModR/M byte now.
1475 uint8_t low_reg1 = LowRegisterBits(raw_reg1);
1476 uint8_t low_reg2 = LowRegisterBits(raw_reg2);
1477 const uint8_t modrm = mod | (low_reg1 << 3) | low_reg2;
1478 code_buffer_.push_back(modrm);
1479 }
1480
EmitRegMemCond(const X86EncodingMap * entry,int32_t raw_reg1,int32_t raw_base,int32_t disp,int32_t cc)1481 void X86Mir2Lir::EmitRegMemCond(const X86EncodingMap* entry, int32_t raw_reg1, int32_t raw_base,
1482 int32_t disp, int32_t cc) {
1483 // Generate prefix and opcode without the condition.
1484 DCHECK_EQ(false, entry->skeleton.r8_form);
1485 EmitPrefixAndOpcode(entry, raw_reg1, NO_REG, raw_base);
1486
1487 // Now add the condition. The last byte of opcode is the one that receives it.
1488 DCHECK_GE(cc, 0);
1489 DCHECK_LT(cc, 16);
1490 code_buffer_.back() += cc;
1491
1492 // Not expecting to have to encode immediate or do anything special for ModR/M since there are
1493 // two registers.
1494 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1495 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1496
1497 uint8_t low_reg1 = LowRegisterBits(raw_reg1);
1498 uint8_t low_base = LowRegisterBits(raw_base);
1499 EmitModrmDisp(low_reg1, low_base, disp);
1500 }
1501
EmitJmp(const X86EncodingMap * entry,int32_t rel)1502 void X86Mir2Lir::EmitJmp(const X86EncodingMap* entry, int32_t rel) {
1503 if (entry->opcode == kX86Jmp8) {
1504 DCHECK(IS_SIMM8(rel));
1505 code_buffer_.push_back(0xEB);
1506 code_buffer_.push_back(rel & 0xFF);
1507 } else if (entry->opcode == kX86Jmp32) {
1508 code_buffer_.push_back(0xE9);
1509 code_buffer_.push_back(rel & 0xFF);
1510 code_buffer_.push_back((rel >> 8) & 0xFF);
1511 code_buffer_.push_back((rel >> 16) & 0xFF);
1512 code_buffer_.push_back((rel >> 24) & 0xFF);
1513 } else if (entry->opcode == kX86Jecxz8) {
1514 DCHECK(IS_SIMM8(rel));
1515 code_buffer_.push_back(0xE3);
1516 code_buffer_.push_back(rel & 0xFF);
1517 } else {
1518 DCHECK(entry->opcode == kX86JmpR);
1519 DCHECK_EQ(false, entry->skeleton.r8_form);
1520 EmitPrefix(entry, NO_REG, NO_REG, rel);
1521 code_buffer_.push_back(entry->skeleton.opcode);
1522 uint8_t low_reg = LowRegisterBits(rel);
1523 uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | low_reg;
1524 code_buffer_.push_back(modrm);
1525 }
1526 }
1527
EmitJcc(const X86EncodingMap * entry,int32_t rel,int32_t cc)1528 void X86Mir2Lir::EmitJcc(const X86EncodingMap* entry, int32_t rel, int32_t cc) {
1529 DCHECK_GE(cc, 0);
1530 DCHECK_LT(cc, 16);
1531 if (entry->opcode == kX86Jcc8) {
1532 DCHECK(IS_SIMM8(rel));
1533 code_buffer_.push_back(0x70 | cc);
1534 code_buffer_.push_back(rel & 0xFF);
1535 } else {
1536 DCHECK(entry->opcode == kX86Jcc32);
1537 code_buffer_.push_back(0x0F);
1538 code_buffer_.push_back(0x80 | cc);
1539 code_buffer_.push_back(rel & 0xFF);
1540 code_buffer_.push_back((rel >> 8) & 0xFF);
1541 code_buffer_.push_back((rel >> 16) & 0xFF);
1542 code_buffer_.push_back((rel >> 24) & 0xFF);
1543 }
1544 }
1545
EmitCallMem(const X86EncodingMap * entry,int32_t raw_base,int32_t disp)1546 void X86Mir2Lir::EmitCallMem(const X86EncodingMap* entry, int32_t raw_base, int32_t disp) {
1547 DCHECK_EQ(false, entry->skeleton.r8_form);
1548 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, raw_base);
1549 uint8_t low_base = LowRegisterBits(raw_base);
1550 EmitModrmDisp(entry->skeleton.modrm_opcode, low_base, disp);
1551 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1552 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1553 }
1554
EmitCallImmediate(const X86EncodingMap * entry,int32_t disp)1555 void X86Mir2Lir::EmitCallImmediate(const X86EncodingMap* entry, int32_t disp) {
1556 DCHECK_EQ(false, entry->skeleton.r8_form);
1557 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG);
1558 DCHECK_EQ(4, entry->skeleton.immediate_bytes);
1559 code_buffer_.push_back(disp & 0xFF);
1560 code_buffer_.push_back((disp >> 8) & 0xFF);
1561 code_buffer_.push_back((disp >> 16) & 0xFF);
1562 code_buffer_.push_back((disp >> 24) & 0xFF);
1563 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1564 }
1565
EmitCallThread(const X86EncodingMap * entry,int32_t disp)1566 void X86Mir2Lir::EmitCallThread(const X86EncodingMap* entry, int32_t disp) {
1567 DCHECK_EQ(false, entry->skeleton.r8_form);
1568 DCHECK_NE(entry->skeleton.prefix1, 0);
1569 EmitPrefixAndOpcode(entry, NO_REG, NO_REG, NO_REG);
1570 EmitModrmThread(entry->skeleton.modrm_opcode);
1571 code_buffer_.push_back(disp & 0xFF);
1572 code_buffer_.push_back((disp >> 8) & 0xFF);
1573 code_buffer_.push_back((disp >> 16) & 0xFF);
1574 code_buffer_.push_back((disp >> 24) & 0xFF);
1575 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1576 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1577 }
1578
EmitPcRel(const X86EncodingMap * entry,int32_t raw_reg,int32_t raw_base_or_table,int32_t raw_index,int scale,int32_t table_or_disp)1579 void X86Mir2Lir::EmitPcRel(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_base_or_table,
1580 int32_t raw_index, int scale, int32_t table_or_disp) {
1581 int disp;
1582 if (entry->opcode == kX86PcRelLoadRA) {
1583 const SwitchTable* tab_rec = UnwrapPointer<SwitchTable>(table_or_disp);
1584 disp = tab_rec->offset - tab_rec->anchor->offset;
1585 } else {
1586 DCHECK(entry->opcode == kX86PcRelAdr);
1587 const EmbeddedData* tab_rec = UnwrapPointer<EmbeddedData>(raw_base_or_table);
1588 disp = tab_rec->offset;
1589 }
1590 if (entry->opcode == kX86PcRelLoadRA) {
1591 DCHECK_EQ(false, entry->skeleton.r8_form);
1592 EmitPrefix(entry, raw_reg, raw_index, raw_base_or_table);
1593 code_buffer_.push_back(entry->skeleton.opcode);
1594 DCHECK_NE(0x0F, entry->skeleton.opcode);
1595 DCHECK_EQ(0, entry->skeleton.extra_opcode1);
1596 DCHECK_EQ(0, entry->skeleton.extra_opcode2);
1597 uint8_t low_reg = LowRegisterBits(raw_reg);
1598 uint8_t modrm = (2 << 6) | (low_reg << 3) | rs_rX86_SP_32.GetRegNum();
1599 code_buffer_.push_back(modrm);
1600 DCHECK_LT(scale, 4);
1601 uint8_t low_base_or_table = LowRegisterBits(raw_base_or_table);
1602 uint8_t low_index = LowRegisterBits(raw_index);
1603 uint8_t sib = (scale << 6) | (low_index << 3) | low_base_or_table;
1604 code_buffer_.push_back(sib);
1605 DCHECK_EQ(0, entry->skeleton.immediate_bytes);
1606 } else {
1607 uint8_t low_reg = LowRegisterBits(raw_reg);
1608 code_buffer_.push_back(entry->skeleton.opcode + low_reg);
1609 }
1610 code_buffer_.push_back(disp & 0xFF);
1611 code_buffer_.push_back((disp >> 8) & 0xFF);
1612 code_buffer_.push_back((disp >> 16) & 0xFF);
1613 code_buffer_.push_back((disp >> 24) & 0xFF);
1614 DCHECK_EQ(0, entry->skeleton.modrm_opcode);
1615 DCHECK_EQ(0, entry->skeleton.ax_opcode);
1616 }
1617
EmitUnimplemented(const X86EncodingMap * entry,LIR * lir)1618 void X86Mir2Lir::EmitUnimplemented(const X86EncodingMap* entry, LIR* lir) {
1619 UNIMPLEMENTED(WARNING) << "encoding kind for " << entry->name << " "
1620 << BuildInsnString(entry->fmt, lir, 0);
1621 for (size_t i = 0; i < GetInsnSize(lir); ++i) {
1622 code_buffer_.push_back(0xCC); // push breakpoint instruction - int 3
1623 }
1624 }
1625
1626 /*
1627 * Assemble the LIR into binary instruction format. Note that we may
1628 * discover that pc-relative displacements may not fit the selected
1629 * instruction. In those cases we will try to substitute a new code
1630 * sequence or request that the trace be shortened and retried.
1631 */
AssembleInstructions(LIR * first_lir_insn,CodeOffset start_addr)1632 AssemblerStatus X86Mir2Lir::AssembleInstructions(LIR* first_lir_insn, CodeOffset start_addr) {
1633 UNUSED(start_addr);
1634 LIR *lir;
1635 AssemblerStatus res = kSuccess; // Assume success
1636
1637 const bool kVerbosePcFixup = false;
1638 for (lir = first_lir_insn; lir != nullptr; lir = NEXT_LIR(lir)) {
1639 if (IsPseudoLirOp(lir->opcode)) {
1640 continue;
1641 }
1642
1643 if (lir->flags.is_nop) {
1644 continue;
1645 }
1646
1647 if (lir->flags.fixup != kFixupNone) {
1648 switch (lir->opcode) {
1649 case kX86Jcc8: {
1650 LIR *target_lir = lir->target;
1651 DCHECK(target_lir != nullptr);
1652 int delta = 0;
1653 CodeOffset pc;
1654 if (IS_SIMM8(lir->operands[0])) {
1655 pc = lir->offset + 2 /* opcode + rel8 */;
1656 } else {
1657 pc = lir->offset + 6 /* 2 byte opcode + rel32 */;
1658 }
1659 CodeOffset target = target_lir->offset;
1660 delta = target - pc;
1661 if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {
1662 if (kVerbosePcFixup) {
1663 LOG(INFO) << "Retry for JCC growth at " << lir->offset
1664 << " delta: " << delta << " old delta: " << lir->operands[0];
1665 }
1666 lir->opcode = kX86Jcc32;
1667 lir->flags.size = GetInsnSize(lir);
1668 DCHECK(lir->u.m.def_mask->Equals(kEncodeAll));
1669 DCHECK(lir->u.m.use_mask->Equals(kEncodeAll));
1670 res = kRetryAll;
1671 }
1672 if (kVerbosePcFixup) {
1673 LOG(INFO) << "Source:";
1674 DumpLIRInsn(lir, 0);
1675 LOG(INFO) << "Target:";
1676 DumpLIRInsn(target_lir, 0);
1677 LOG(INFO) << "Delta " << delta;
1678 }
1679 lir->operands[0] = delta;
1680 break;
1681 }
1682 case kX86Jcc32: {
1683 LIR *target_lir = lir->target;
1684 DCHECK(target_lir != nullptr);
1685 CodeOffset pc = lir->offset + 6 /* 2 byte opcode + rel32 */;
1686 CodeOffset target = target_lir->offset;
1687 int delta = target - pc;
1688 if (kVerbosePcFixup) {
1689 LOG(INFO) << "Source:";
1690 DumpLIRInsn(lir, 0);
1691 LOG(INFO) << "Target:";
1692 DumpLIRInsn(target_lir, 0);
1693 LOG(INFO) << "Delta " << delta;
1694 }
1695 lir->operands[0] = delta;
1696 break;
1697 }
1698 case kX86Jecxz8: {
1699 LIR *target_lir = lir->target;
1700 DCHECK(target_lir != nullptr);
1701 CodeOffset pc;
1702 pc = lir->offset + 2; // opcode + rel8
1703 CodeOffset target = target_lir->offset;
1704 int delta = target - pc;
1705 lir->operands[0] = delta;
1706 DCHECK(IS_SIMM8(delta));
1707 break;
1708 }
1709 case kX86Jmp8: {
1710 LIR *target_lir = lir->target;
1711 DCHECK(target_lir != nullptr);
1712 int delta = 0;
1713 CodeOffset pc;
1714 if (IS_SIMM8(lir->operands[0])) {
1715 pc = lir->offset + 2 /* opcode + rel8 */;
1716 } else {
1717 pc = lir->offset + 5 /* opcode + rel32 */;
1718 }
1719 CodeOffset target = target_lir->offset;
1720 delta = target - pc;
1721 if (!(cu_->disable_opt & (1 << kSafeOptimizations)) && delta == 0) {
1722 // Useless branch
1723 NopLIR(lir);
1724 if (kVerbosePcFixup) {
1725 LOG(INFO) << "Retry for useless branch at " << lir->offset;
1726 }
1727 res = kRetryAll;
1728 } else if (IS_SIMM8(delta) != IS_SIMM8(lir->operands[0])) {
1729 if (kVerbosePcFixup) {
1730 LOG(INFO) << "Retry for JMP growth at " << lir->offset;
1731 }
1732 lir->opcode = kX86Jmp32;
1733 lir->flags.size = GetInsnSize(lir);
1734 DCHECK(lir->u.m.def_mask->Equals(kEncodeAll));
1735 DCHECK(lir->u.m.use_mask->Equals(kEncodeAll));
1736 res = kRetryAll;
1737 }
1738 lir->operands[0] = delta;
1739 break;
1740 }
1741 case kX86Jmp32: {
1742 LIR *target_lir = lir->target;
1743 DCHECK(target_lir != nullptr);
1744 CodeOffset pc = lir->offset + 5 /* opcode + rel32 */;
1745 CodeOffset target = target_lir->offset;
1746 int delta = target - pc;
1747 lir->operands[0] = delta;
1748 break;
1749 }
1750 default:
1751 if (lir->flags.fixup == kFixupLoad) {
1752 LIR *target_lir = lir->target;
1753 DCHECK(target_lir != nullptr);
1754 CodeOffset target = target_lir->offset;
1755 // Handle 64 bit RIP addressing.
1756 if (lir->operands[1] == kRIPReg) {
1757 // Offset is relative to next instruction.
1758 lir->operands[2] = target - (lir->offset + lir->flags.size);
1759 } else {
1760 const LIR* anchor = UnwrapPointer<LIR>(lir->operands[4]);
1761 lir->operands[2] = target - anchor->offset;
1762 int newSize = GetInsnSize(lir);
1763 if (newSize != lir->flags.size) {
1764 lir->flags.size = newSize;
1765 res = kRetryAll;
1766 }
1767 }
1768 } else if (lir->flags.fixup == kFixupSwitchTable) {
1769 DCHECK(cu_->target64);
1770 DCHECK_EQ(lir->opcode, kX86Lea64RM) << "Unknown instruction: " << X86Mir2Lir::EncodingMap[lir->opcode].name;
1771 DCHECK_EQ(lir->operands[1], static_cast<int>(kRIPReg));
1772 // Grab the target offset from the saved data.
1773 const EmbeddedData* tab_rec = UnwrapPointer<Mir2Lir::EmbeddedData>(lir->operands[4]);
1774 CodeOffset target = tab_rec->offset;
1775 // Handle 64 bit RIP addressing.
1776 // Offset is relative to next instruction.
1777 lir->operands[2] = target - (lir->offset + lir->flags.size);
1778 }
1779 break;
1780 }
1781 }
1782
1783 /*
1784 * If one of the pc-relative instructions expanded we'll have
1785 * to make another pass. Don't bother to fully assemble the
1786 * instruction.
1787 */
1788 if (res != kSuccess) {
1789 continue;
1790 }
1791 CHECK_EQ(static_cast<size_t>(lir->offset), code_buffer_.size());
1792 const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];
1793 size_t starting_cbuf_size = code_buffer_.size();
1794 switch (entry->kind) {
1795 case kData: // 4 bytes of data
1796 code_buffer_.push_back(lir->operands[0]);
1797 break;
1798 case kNullary: // 1 byte of opcode and possible prefixes.
1799 EmitNullary(entry);
1800 break;
1801 case kRegOpcode: // lir operands - 0: reg
1802 EmitOpRegOpcode(entry, lir->operands[0]);
1803 break;
1804 case kReg: // lir operands - 0: reg
1805 EmitOpReg(entry, lir->operands[0]);
1806 break;
1807 case kMem: // lir operands - 0: base, 1: disp
1808 EmitOpMem(entry, lir->operands[0], lir->operands[1]);
1809 break;
1810 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp
1811 EmitOpArray(entry, lir->operands[0], lir->operands[1], lir->operands[2], lir->operands[3]);
1812 break;
1813 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg
1814 EmitMemReg(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1815 break;
1816 case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate
1817 EmitMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1818 break;
1819 case kArrayImm: // lir operands - 0: base, 1: index, 2: disp, 3:scale, 4:immediate
1820 EmitArrayImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1821 lir->operands[3], lir->operands[4]);
1822 break;
1823 case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
1824 EmitArrayReg(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1825 lir->operands[3], lir->operands[4]);
1826 break;
1827 case kRegMem: // lir operands - 0: reg, 1: base, 2: disp
1828 EmitRegMem(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1829 break;
1830 case kRegArray: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp
1831 EmitRegArray(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1832 lir->operands[3], lir->operands[4]);
1833 break;
1834 case kRegThread: // lir operands - 0: reg, 1: disp
1835 EmitRegThread(entry, lir->operands[0], lir->operands[1]);
1836 break;
1837 case kRegReg: // lir operands - 0: reg1, 1: reg2
1838 EmitRegReg(entry, lir->operands[0], lir->operands[1]);
1839 break;
1840 case kRegRegStore: // lir operands - 0: reg2, 1: reg1
1841 EmitRegReg(entry, lir->operands[1], lir->operands[0]);
1842 break;
1843 case kMemRegImm: // lir operands - 0: base, 1: disp, 2: reg 3: immediate
1844 EmitMemRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1845 lir->operands[3]);
1846 break;
1847 case kRegRegImm: // lir operands - 0: reg1, 1: reg2, 2: imm
1848 EmitRegRegImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1849 break;
1850 case kRegRegImmStore: // lir operands - 0: reg2, 1: reg1, 2: imm
1851 EmitRegRegImm(entry, lir->operands[1], lir->operands[0], lir->operands[2]);
1852 break;
1853 case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm
1854 EmitRegMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1855 lir->operands[3]);
1856 break;
1857 case kRegImm: // lir operands - 0: reg, 1: immediate
1858 EmitRegImm(entry, lir->operands[0], lir->operands[1]);
1859 break;
1860 case kThreadImm: // lir operands - 0: disp, 1: immediate
1861 EmitThreadImm(entry, lir->operands[0], lir->operands[1]);
1862 break;
1863 case kMovRegImm: // lir operands - 0: reg, 1: immediate
1864 EmitMovRegImm(entry, lir->operands[0], lir->operands[1]);
1865 break;
1866 case kMovRegQuadImm: {
1867 int64_t value = static_cast<int64_t>(static_cast<int64_t>(lir->operands[1]) << 32 |
1868 static_cast<uint32_t>(lir->operands[2]));
1869 EmitMovRegImm(entry, lir->operands[0], value);
1870 }
1871 break;
1872 case kShiftRegImm: // lir operands - 0: reg, 1: immediate
1873 EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);
1874 break;
1875 case kShiftMemImm: // lir operands - 0: base, 1: disp, 2:immediate
1876 EmitShiftMemImm(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1877 break;
1878 case kShiftRegCl: // lir operands - 0: reg, 1: cl
1879 EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);
1880 break;
1881 case kShiftMemCl: // lir operands - 0: base, 1:displacement, 2: cl
1882 EmitShiftMemCl(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1883 break;
1884 case kShiftRegRegCl: // lir operands - 0: reg1, 1: reg2, 2: cl
1885 EmitShiftRegRegCl(entry, lir->operands[1], lir->operands[0], lir->operands[2]);
1886 break;
1887 case kRegCond: // lir operands - 0: reg, 1: condition
1888 EmitRegCond(entry, lir->operands[0], lir->operands[1]);
1889 break;
1890 case kMemCond: // lir operands - 0: base, 1: displacement, 2: condition
1891 EmitMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1892 break;
1893 case kRegRegCond: // lir operands - 0: reg, 1: reg, 2: condition
1894 EmitRegRegCond(entry, lir->operands[0], lir->operands[1], lir->operands[2]);
1895 break;
1896 case kRegMemCond: // lir operands - 0: reg, 1: reg, displacement, 3: condition
1897 EmitRegMemCond(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1898 lir->operands[3]);
1899 break;
1900 case kJmp: // lir operands - 0: rel
1901 if (entry->opcode == kX86JmpT) {
1902 // This works since the instruction format for jmp and call is basically the same and
1903 // EmitCallThread loads opcode info.
1904 EmitCallThread(entry, lir->operands[0]);
1905 } else {
1906 EmitJmp(entry, lir->operands[0]);
1907 }
1908 break;
1909 case kJcc: // lir operands - 0: rel, 1: CC, target assigned
1910 EmitJcc(entry, lir->operands[0], lir->operands[1]);
1911 break;
1912 case kCall:
1913 switch (entry->opcode) {
1914 case kX86CallI: // lir operands - 0: disp
1915 EmitCallImmediate(entry, lir->operands[0]);
1916 break;
1917 case kX86CallM: // lir operands - 0: base, 1: disp
1918 EmitCallMem(entry, lir->operands[0], lir->operands[1]);
1919 break;
1920 case kX86CallT: // lir operands - 0: disp
1921 EmitCallThread(entry, lir->operands[0]);
1922 break;
1923 default:
1924 EmitUnimplemented(entry, lir);
1925 break;
1926 }
1927 break;
1928 case kPcRel: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: table
1929 EmitPcRel(entry, lir->operands[0], lir->operands[1], lir->operands[2],
1930 lir->operands[3], lir->operands[4]);
1931 break;
1932 case kNop: // TODO: these instruction kinds are missing implementations.
1933 case kThreadReg:
1934 case kRegArrayImm:
1935 case kShiftArrayImm:
1936 case kShiftArrayCl:
1937 case kArrayCond:
1938 case kUnimplemented:
1939 EmitUnimplemented(entry, lir);
1940 break;
1941 }
1942 DCHECK_EQ(lir->flags.size, GetInsnSize(lir));
1943 CHECK_EQ(lir->flags.size, code_buffer_.size() - starting_cbuf_size)
1944 << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;
1945 }
1946 return res;
1947 }
1948
1949 // LIR offset assignment.
1950 // TODO: consolidate w/ Arm assembly mechanism.
AssignInsnOffsets()1951 int X86Mir2Lir::AssignInsnOffsets() {
1952 LIR* lir;
1953 int offset = 0;
1954
1955 for (lir = first_lir_insn_; lir != nullptr; lir = NEXT_LIR(lir)) {
1956 lir->offset = offset;
1957 if (LIKELY(!IsPseudoLirOp(lir->opcode))) {
1958 if (!lir->flags.is_nop) {
1959 offset += lir->flags.size;
1960 }
1961 } else if (UNLIKELY(lir->opcode == kPseudoPseudoAlign4)) {
1962 if (offset & 0x2) {
1963 offset += 2;
1964 lir->operands[0] = 1;
1965 } else {
1966 lir->operands[0] = 0;
1967 }
1968 }
1969 /* Pseudo opcodes don't consume space */
1970 }
1971 return offset;
1972 }
1973
1974 /*
1975 * Walk the compilation unit and assign offsets to instructions
1976 * and literals and compute the total size of the compiled unit.
1977 * TODO: consolidate w/ Arm assembly mechanism.
1978 */
AssignOffsets()1979 void X86Mir2Lir::AssignOffsets() {
1980 int offset = AssignInsnOffsets();
1981
1982 if (const_vectors_ != nullptr) {
1983 // Vector literals must be 16-byte aligned. The header that is placed
1984 // in the code section causes misalignment so we take it into account.
1985 // Otherwise, we are sure that for x86 method is aligned to 16.
1986 DCHECK_EQ(GetInstructionSetAlignment(cu_->instruction_set), 16u);
1987 uint32_t bytes_to_fill = (0x10 - ((offset + sizeof(OatQuickMethodHeader)) & 0xF)) & 0xF;
1988 offset += bytes_to_fill;
1989
1990 // Now assign each literal the right offset.
1991 for (LIR *p = const_vectors_; p != nullptr; p = p->next) {
1992 p->offset = offset;
1993 offset += 16;
1994 }
1995 }
1996
1997 /* Const values have to be word aligned */
1998 offset = RoundUp(offset, 4);
1999
2000 /* Set up offsets for literals */
2001 data_offset_ = offset;
2002
2003 offset = AssignLiteralOffset(offset);
2004
2005 offset = AssignSwitchTablesOffset(offset);
2006
2007 offset = AssignFillArrayDataOffset(offset);
2008
2009 total_size_ = offset;
2010 }
2011
2012 /*
2013 * Go over each instruction in the list and calculate the offset from the top
2014 * before sending them off to the assembler. If out-of-range branch distance is
2015 * seen rearrange the instructions a bit to correct it.
2016 * TODO: consolidate w/ Arm assembly mechanism.
2017 */
AssembleLIR()2018 void X86Mir2Lir::AssembleLIR() {
2019 cu_->NewTimingSplit("Assemble");
2020
2021 // We will remove the method address if we never ended up using it
2022 if (pc_rel_base_reg_.Valid() && !pc_rel_base_reg_used_) {
2023 if (kIsDebugBuild) {
2024 LOG(WARNING) << "PC-relative addressing base promoted but unused in "
2025 << PrettyMethod(cu_->method_idx, *cu_->dex_file);
2026 }
2027 setup_pc_rel_base_reg_->flags.is_nop = true;
2028 NEXT_LIR(setup_pc_rel_base_reg_)->flags.is_nop = true;
2029 }
2030
2031 AssignOffsets();
2032 int assembler_retries = 0;
2033 /*
2034 * Assemble here. Note that we generate code with optimistic assumptions
2035 * and if found now to work, we'll have to redo the sequence and retry.
2036 */
2037
2038 while (true) {
2039 AssemblerStatus res = AssembleInstructions(first_lir_insn_, 0);
2040 if (res == kSuccess) {
2041 break;
2042 } else {
2043 assembler_retries++;
2044 if (assembler_retries > MAX_ASSEMBLER_RETRIES) {
2045 CodegenDump();
2046 LOG(FATAL) << "Assembler error - too many retries";
2047 }
2048 // Redo offsets and try again
2049 AssignOffsets();
2050 code_buffer_.clear();
2051 }
2052 }
2053
2054 // Install literals
2055 InstallLiteralPools();
2056
2057 // Install switch tables
2058 InstallSwitchTables();
2059
2060 // Install fill array data
2061 InstallFillArrayData();
2062
2063 // Create the mapping table and native offset to reference map.
2064 cu_->NewTimingSplit("PcMappingTable");
2065 CreateMappingTables();
2066
2067 cu_->NewTimingSplit("GcMap");
2068 CreateNativeGcMap();
2069 }
2070
2071 } // namespace art
2072