Searched defs:FirstReg (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1190 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1192 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 491 unsigned FirstReg = 0; in CreateRegs() local
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| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 485 unsigned FirstReg = 0; in ScanInstruction() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 677 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3570 const Argument *FuncArg, unsigned FirstReg, unsigned LastReg, in copyByValRegs()
3619 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
3766 unsigned FirstReg = 0; in HandleByVal() local
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1149 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList64Operands() local
1160 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList128Operands() local
2849 int64_t FirstReg = tryMatchVectorRegister(Kind, true); in parseVectorList() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 2027 unsigned FirstReg = MI->getOperand(RegListIdx).getReg(); in tryFoldSPUpdateIntoPushPop() local
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 3665 unsigned FirstReg = Reg; in parseVectorList() local
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