1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares codegen opcodes and related utilities. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_CODEGEN_ISDOPCODES_H 15 #define LLVM_CODEGEN_ISDOPCODES_H 16 17 namespace llvm { 18 19 /// ISD namespace - This namespace contains an enum which represents all of the 20 /// SelectionDAG node types and value types. 21 /// 22 namespace ISD { 23 24 //===--------------------------------------------------------------------===// 25 /// ISD::NodeType enum - This enum defines the target-independent operators 26 /// for a SelectionDAG. 27 /// 28 /// Targets may also define target-dependent operator codes for SDNodes. For 29 /// example, on x86, these are the enum values in the X86ISD namespace. 30 /// Targets should aim to use target-independent operators to model their 31 /// instruction sets as much as possible, and only use target-dependent 32 /// operators when they have special requirements. 33 /// 34 /// Finally, during and after selection proper, SNodes may use special 35 /// operator codes that correspond directly with MachineInstr opcodes. These 36 /// are used to represent selected instructions. See the isMachineOpcode() 37 /// and getMachineOpcode() member functions of SDNode. 38 /// 39 enum NodeType { 40 /// DELETED_NODE - This is an illegal value that is used to catch 41 /// errors. This opcode is not a legal opcode for any node. 42 DELETED_NODE, 43 44 /// EntryToken - This is the marker used to indicate the start of a region. 45 EntryToken, 46 47 /// TokenFactor - This node takes multiple tokens as input and produces a 48 /// single token result. This is used to represent the fact that the operand 49 /// operators are independent of each other. 50 TokenFactor, 51 52 /// AssertSext, AssertZext - These nodes record if a register contains a 53 /// value that has already been zero or sign extended from a narrower type. 54 /// These nodes take two operands. The first is the node that has already 55 /// been extended, and the second is a value type node indicating the width 56 /// of the extension 57 AssertSext, AssertZext, 58 59 /// Various leaf nodes. 60 BasicBlock, VALUETYPE, CONDCODE, Register, RegisterMask, 61 Constant, ConstantFP, 62 GlobalAddress, GlobalTLSAddress, FrameIndex, 63 JumpTable, ConstantPool, ExternalSymbol, BlockAddress, 64 65 /// The address of the GOT 66 GLOBAL_OFFSET_TABLE, 67 68 /// FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and 69 /// llvm.returnaddress on the DAG. These nodes take one operand, the index 70 /// of the frame or return address to return. An index of zero corresponds 71 /// to the current function's frame or return address, an index of one to 72 /// the parent's frame or return address, and so on. 73 FRAMEADDR, RETURNADDR, 74 75 /// FRAME_ALLOC_RECOVER - Represents the llvm.framerecover 76 /// intrinsic. Materializes the offset from the frame pointer of another 77 /// function to the result of llvm.frameallocate. 78 FRAME_ALLOC_RECOVER, 79 80 /// READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on 81 /// the DAG, which implements the named register global variables extension. 82 READ_REGISTER, 83 WRITE_REGISTER, 84 85 /// FRAME_TO_ARGS_OFFSET - This node represents offset from frame pointer to 86 /// first (possible) on-stack argument. This is needed for correct stack 87 /// adjustment during unwind. 88 FRAME_TO_ARGS_OFFSET, 89 90 /// OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 91 /// 'eh_return' gcc dwarf builtin, which is used to return from 92 /// exception. The general meaning is: adjust stack by OFFSET and pass 93 /// execution to HANDLER. Many platform-related details also :) 94 EH_RETURN, 95 96 /// RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) 97 /// This corresponds to the eh.sjlj.setjmp intrinsic. 98 /// It takes an input chain and a pointer to the jump buffer as inputs 99 /// and returns an outchain. 100 EH_SJLJ_SETJMP, 101 102 /// OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) 103 /// This corresponds to the eh.sjlj.longjmp intrinsic. 104 /// It takes an input chain and a pointer to the jump buffer as inputs 105 /// and returns an outchain. 106 EH_SJLJ_LONGJMP, 107 108 /// TargetConstant* - Like Constant*, but the DAG does not do any folding, 109 /// simplification, or lowering of the constant. They are used for constants 110 /// which are known to fit in the immediate fields of their users, or for 111 /// carrying magic numbers which are not values which need to be 112 /// materialized in registers. 113 TargetConstant, 114 TargetConstantFP, 115 116 /// TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or 117 /// anything else with this node, and this is valid in the target-specific 118 /// dag, turning into a GlobalAddress operand. 119 TargetGlobalAddress, 120 TargetGlobalTLSAddress, 121 TargetFrameIndex, 122 TargetJumpTable, 123 TargetConstantPool, 124 TargetExternalSymbol, 125 TargetBlockAddress, 126 127 /// TargetIndex - Like a constant pool entry, but with completely 128 /// target-dependent semantics. Holds target flags, a 32-bit index, and a 129 /// 64-bit index. Targets can use this however they like. 130 TargetIndex, 131 132 /// RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) 133 /// This node represents a target intrinsic function with no side effects. 134 /// The first operand is the ID number of the intrinsic from the 135 /// llvm::Intrinsic namespace. The operands to the intrinsic follow. The 136 /// node returns the result of the intrinsic. 137 INTRINSIC_WO_CHAIN, 138 139 /// RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) 140 /// This node represents a target intrinsic function with side effects that 141 /// returns a result. The first operand is a chain pointer. The second is 142 /// the ID number of the intrinsic from the llvm::Intrinsic namespace. The 143 /// operands to the intrinsic follow. The node has two results, the result 144 /// of the intrinsic and an output chain. 145 INTRINSIC_W_CHAIN, 146 147 /// OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) 148 /// This node represents a target intrinsic function with side effects that 149 /// does not return a result. The first operand is a chain pointer. The 150 /// second is the ID number of the intrinsic from the llvm::Intrinsic 151 /// namespace. The operands to the intrinsic follow. 152 INTRINSIC_VOID, 153 154 /// CopyToReg - This node has three operands: a chain, a register number to 155 /// set to this value, and a value. 156 CopyToReg, 157 158 /// CopyFromReg - This node indicates that the input value is a virtual or 159 /// physical register that is defined outside of the scope of this 160 /// SelectionDAG. The register is available from the RegisterSDNode object. 161 CopyFromReg, 162 163 /// UNDEF - An undefined node. 164 UNDEF, 165 166 /// EXTRACT_ELEMENT - This is used to get the lower or upper (determined by 167 /// a Constant, which is required to be operand #1) half of the integer or 168 /// float value specified as operand #0. This is only for use before 169 /// legalization, for values that will be broken into multiple registers. 170 EXTRACT_ELEMENT, 171 172 /// BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways. 173 /// Given two values of the same integer value type, this produces a value 174 /// twice as big. Like EXTRACT_ELEMENT, this can only be used before 175 /// legalization. 176 BUILD_PAIR, 177 178 /// MERGE_VALUES - This node takes multiple discrete operands and returns 179 /// them all as its individual results. This nodes has exactly the same 180 /// number of inputs and outputs. This node is useful for some pieces of the 181 /// code generator that want to think about a single node with multiple 182 /// results, not multiple nodes. 183 MERGE_VALUES, 184 185 /// Simple integer binary arithmetic operators. 186 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, 187 188 /// SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing 189 /// a signed/unsigned value of type i[2*N], and return the full value as 190 /// two results, each of type iN. 191 SMUL_LOHI, UMUL_LOHI, 192 193 /// SDIVREM/UDIVREM - Divide two integers and produce both a quotient and 194 /// remainder result. 195 SDIVREM, UDIVREM, 196 197 /// CARRY_FALSE - This node is used when folding other nodes, 198 /// like ADDC/SUBC, which indicate the carry result is always false. 199 CARRY_FALSE, 200 201 /// Carry-setting nodes for multiple precision addition and subtraction. 202 /// These nodes take two operands of the same value type, and produce two 203 /// results. The first result is the normal add or sub result, the second 204 /// result is the carry flag result. 205 ADDC, SUBC, 206 207 /// Carry-using nodes for multiple precision addition and subtraction. These 208 /// nodes take three operands: The first two are the normal lhs and rhs to 209 /// the add or sub, and the third is the input carry flag. These nodes 210 /// produce two results; the normal result of the add or sub, and the output 211 /// carry flag. These nodes both read and write a carry flag to allow them 212 /// to them to be chained together for add and sub of arbitrarily large 213 /// values. 214 ADDE, SUBE, 215 216 /// RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition. 217 /// These nodes take two operands: the normal LHS and RHS to the add. They 218 /// produce two results: the normal result of the add, and a boolean that 219 /// indicates if an overflow occurred (*not* a flag, because it may be store 220 /// to memory, etc.). If the type of the boolean is not i1 then the high 221 /// bits conform to getBooleanContents. 222 /// These nodes are generated from llvm.[su]add.with.overflow intrinsics. 223 SADDO, UADDO, 224 225 /// Same for subtraction. 226 SSUBO, USUBO, 227 228 /// Same for multiplication. 229 SMULO, UMULO, 230 231 /// Simple binary floating point operators. 232 FADD, FSUB, FMUL, FDIV, FREM, 233 234 /// FMA - Perform a * b + c with no intermediate rounding step. 235 FMA, 236 237 /// FMAD - Perform a * b + c, while getting the same result as the 238 /// separately rounded operations. 239 FMAD, 240 241 /// FCOPYSIGN(X, Y) - Return the value of X with the sign of Y. NOTE: This 242 /// DAG node does not require that X and Y have the same type, just that the 243 /// are both floating point. X and the result must have the same type. 244 /// FCOPYSIGN(f32, f64) is allowed. 245 FCOPYSIGN, 246 247 /// INT = FGETSIGN(FP) - Return the sign bit of the specified floating point 248 /// value as an integer 0/1 value. 249 FGETSIGN, 250 251 /// BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a vector with the 252 /// specified, possibly variable, elements. The number of elements is 253 /// required to be a power of two. The types of the operands must all be 254 /// the same and must match the vector element type, except that integer 255 /// types are allowed to be larger than the element type, in which case 256 /// the operands are implicitly truncated. 257 BUILD_VECTOR, 258 259 /// INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element 260 /// at IDX replaced with VAL. If the type of VAL is larger than the vector 261 /// element type then VAL is truncated before replacement. 262 INSERT_VECTOR_ELT, 263 264 /// EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR 265 /// identified by the (potentially variable) element number IDX. If the 266 /// return type is an integer type larger than the element type of the 267 /// vector, the result is extended to the width of the return type. 268 EXTRACT_VECTOR_ELT, 269 270 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 271 /// vector type with the same length and element type, this produces a 272 /// concatenated vector result value, with length equal to the sum of the 273 /// lengths of the input vectors. 274 CONCAT_VECTORS, 275 276 /// INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector 277 /// with VECTOR2 inserted into VECTOR1 at the (potentially 278 /// variable) element number IDX, which must be a multiple of the 279 /// VECTOR2 vector length. The elements of VECTOR1 starting at 280 /// IDX are overwritten with VECTOR2. Elements IDX through 281 /// vector_length(VECTOR2) must be valid VECTOR1 indices. 282 INSERT_SUBVECTOR, 283 284 /// EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR (an 285 /// vector value) starting with the element number IDX, which must be a 286 /// constant multiple of the result vector length. 287 EXTRACT_SUBVECTOR, 288 289 /// VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as 290 /// VEC1/VEC2. A VECTOR_SHUFFLE node also contains an array of constant int 291 /// values that indicate which value (or undef) each result element will 292 /// get. These constant ints are accessible through the 293 /// ShuffleVectorSDNode class. This is quite similar to the Altivec 294 /// 'vperm' instruction, except that the indices must be constants and are 295 /// in terms of the element size of VEC1/VEC2, not in terms of bytes. 296 VECTOR_SHUFFLE, 297 298 /// SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a 299 /// scalar value into element 0 of the resultant vector type. The top 300 /// elements 1 to N-1 of the N-element vector are undefined. The type 301 /// of the operand must match the vector element type, except when they 302 /// are integer types. In this case the operand is allowed to be wider 303 /// than the vector element type, and is implicitly truncated to it. 304 SCALAR_TO_VECTOR, 305 306 /// MULHU/MULHS - Multiply high - Multiply two integers of type iN, 307 /// producing an unsigned/signed value of type i[2*N], then return the top 308 /// part. 309 MULHU, MULHS, 310 311 /// Bitwise operators - logical and, logical or, logical xor. 312 AND, OR, XOR, 313 314 /// Shift and rotation operations. After legalization, the type of the 315 /// shift amount is known to be TLI.getShiftAmountTy(). Before legalization 316 /// the shift amount can be any type, but care must be taken to ensure it is 317 /// large enough. TLI.getShiftAmountTy() is i8 on some targets, but before 318 /// legalization, types like i1024 can occur and i8 doesn't have enough bits 319 /// to represent the shift amount. 320 /// When the 1st operand is a vector, the shift amount must be in the same 321 /// type. (TLI.getShiftAmountTy() will return the same type when the input 322 /// type is a vector.) 323 SHL, SRA, SRL, ROTL, ROTR, 324 325 /// Byte Swap and Counting operators. 326 BSWAP, CTTZ, CTLZ, CTPOP, 327 328 /// Bit counting operators with an undefined result for zero inputs. 329 CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF, 330 331 /// Select(COND, TRUEVAL, FALSEVAL). If the type of the boolean COND is not 332 /// i1 then the high bits must conform to getBooleanContents. 333 SELECT, 334 335 /// Select with a vector condition (op #0) and two vector operands (ops #1 336 /// and #2), returning a vector result. All vectors have the same length. 337 /// Much like the scalar select and setcc, each bit in the condition selects 338 /// whether the corresponding result element is taken from op #1 or op #2. 339 /// At first, the VSELECT condition is of vXi1 type. Later, targets may 340 /// change the condition type in order to match the VSELECT node using a 341 /// pattern. The condition follows the BooleanContent format of the target. 342 VSELECT, 343 344 /// Select with condition operator - This selects between a true value and 345 /// a false value (ops #2 and #3) based on the boolean result of comparing 346 /// the lhs and rhs (ops #0 and #1) of a conditional expression with the 347 /// condition code in op #4, a CondCodeSDNode. 348 SELECT_CC, 349 350 /// SetCC operator - This evaluates to a true value iff the condition is 351 /// true. If the result value type is not i1 then the high bits conform 352 /// to getBooleanContents. The operands to this are the left and right 353 /// operands to compare (ops #0, and #1) and the condition code to compare 354 /// them with (op #2) as a CondCodeSDNode. If the operands are vector types 355 /// then the result type must also be a vector type. 356 SETCC, 357 358 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded 359 /// integer shift operations, just like ADD/SUB_PARTS. The operation 360 /// ordering is: 361 /// [Lo,Hi] = op [LoLHS,HiLHS], Amt 362 SHL_PARTS, SRA_PARTS, SRL_PARTS, 363 364 /// Conversion operators. These are all single input single output 365 /// operations. For all of these, the result type must be strictly 366 /// wider or narrower (depending on the operation) than the source 367 /// type. 368 369 /// SIGN_EXTEND - Used for integer types, replicating the sign bit 370 /// into new bits. 371 SIGN_EXTEND, 372 373 /// ZERO_EXTEND - Used for integer types, zeroing the new bits. 374 ZERO_EXTEND, 375 376 /// ANY_EXTEND - Used for integer types. The high bits are undefined. 377 ANY_EXTEND, 378 379 /// TRUNCATE - Completely drop the high bits. 380 TRUNCATE, 381 382 /// [SU]INT_TO_FP - These operators convert integers (whose interpreted sign 383 /// depends on the first letter) to floating point. 384 SINT_TO_FP, 385 UINT_TO_FP, 386 387 /// SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to 388 /// sign extend a small value in a large integer register (e.g. sign 389 /// extending the low 8 bits of a 32-bit register to fill the top 24 bits 390 /// with the 7th bit). The size of the smaller type is indicated by the 1th 391 /// operand, a ValueType node. 392 SIGN_EXTEND_INREG, 393 394 /// ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an 395 /// in-register any-extension of the low lanes of an integer vector. The 396 /// result type must have fewer elements than the operand type, and those 397 /// elements must be larger integer types such that the total size of the 398 /// operand type and the result type match. Each of the low operand 399 /// elements is any-extended into the corresponding, wider result 400 /// elements with the high bits becoming undef. 401 ANY_EXTEND_VECTOR_INREG, 402 403 /// SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an 404 /// in-register sign-extension of the low lanes of an integer vector. The 405 /// result type must have fewer elements than the operand type, and those 406 /// elements must be larger integer types such that the total size of the 407 /// operand type and the result type match. Each of the low operand 408 /// elements is sign-extended into the corresponding, wider result 409 /// elements. 410 // FIXME: The SIGN_EXTEND_INREG node isn't specifically limited to 411 // scalars, but it also doesn't handle vectors well. Either it should be 412 // restricted to scalars or this node (and its handling) should be merged 413 // into it. 414 SIGN_EXTEND_VECTOR_INREG, 415 416 /// ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an 417 /// in-register zero-extension of the low lanes of an integer vector. The 418 /// result type must have fewer elements than the operand type, and those 419 /// elements must be larger integer types such that the total size of the 420 /// operand type and the result type match. Each of the low operand 421 /// elements is zero-extended into the corresponding, wider result 422 /// elements. 423 ZERO_EXTEND_VECTOR_INREG, 424 425 /// FP_TO_[US]INT - Convert a floating point value to a signed or unsigned 426 /// integer. 427 FP_TO_SINT, 428 FP_TO_UINT, 429 430 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 431 /// down to the precision of the destination VT. TRUNC is a flag, which is 432 /// always an integer that is zero or one. If TRUNC is 0, this is a 433 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 434 /// value of Y. 435 /// 436 /// The TRUNC = 1 case is used in cases where we know that the value will 437 /// not be modified by the node, because Y is not using any of the extra 438 /// precision of source type. This allows certain transformations like 439 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 440 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 441 FP_ROUND, 442 443 /// FLT_ROUNDS_ - Returns current rounding mode: 444 /// -1 Undefined 445 /// 0 Round to 0 446 /// 1 Round to nearest 447 /// 2 Round to +inf 448 /// 3 Round to -inf 449 FLT_ROUNDS_, 450 451 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and 452 /// rounds it to a floating point value. It then promotes it and returns it 453 /// in a register of the same size. This operation effectively just 454 /// discards excess precision. The type to round down to is specified by 455 /// the VT operand, a VTSDNode. 456 FP_ROUND_INREG, 457 458 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type. 459 FP_EXTEND, 460 461 /// BITCAST - This operator converts between integer, vector and FP 462 /// values, as if the value was stored to memory with one type and loaded 463 /// from the same address with the other type (or equivalently for vector 464 /// format conversions, etc). The source and result are required to have 465 /// the same bit size (e.g. f32 <-> i32). This can also be used for 466 /// int-to-int or fp-to-fp conversions, but that is a noop, deleted by 467 /// getNode(). 468 BITCAST, 469 470 /// ADDRSPACECAST - This operator converts between pointers of different 471 /// address spaces. 472 ADDRSPACECAST, 473 474 /// CONVERT_RNDSAT - This operator is used to support various conversions 475 /// between various types (float, signed, unsigned and vectors of those 476 /// types) with rounding and saturation. NOTE: Avoid using this operator as 477 /// most target don't support it and the operator might be removed in the 478 /// future. It takes the following arguments: 479 /// 0) value 480 /// 1) dest type (type to convert to) 481 /// 2) src type (type to convert from) 482 /// 3) rounding imm 483 /// 4) saturation imm 484 /// 5) ISD::CvtCode indicating the type of conversion to do 485 CONVERT_RNDSAT, 486 487 /// FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions 488 /// and truncation for half-precision (16 bit) floating numbers. These nodes 489 /// form a semi-softened interface for dealing with f16 (as an i16), which 490 /// is often a storage-only type but has native conversions. 491 FP16_TO_FP, FP_TO_FP16, 492 493 /// FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 494 /// FLOG, FLOG2, FLOG10, FEXP, FEXP2, 495 /// FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR - Perform various unary 496 /// floating point operations. These are inspired by libm. 497 FNEG, FABS, FSQRT, FSIN, FCOS, FPOWI, FPOW, 498 FLOG, FLOG2, FLOG10, FEXP, FEXP2, 499 FCEIL, FTRUNC, FRINT, FNEARBYINT, FROUND, FFLOOR, 500 FMINNUM, FMAXNUM, 501 502 /// FSINCOS - Compute both fsin and fcos as a single operation. 503 FSINCOS, 504 505 /// LOAD and STORE have token chains as their first operand, then the same 506 /// operands as an LLVM load/store instruction, then an offset node that 507 /// is added / subtracted from the base pointer to form the address (for 508 /// indexed memory ops). 509 LOAD, STORE, 510 511 /// DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned 512 /// to a specified boundary. This node always has two return values: a new 513 /// stack pointer value and a chain. The first operand is the token chain, 514 /// the second is the number of bytes to allocate, and the third is the 515 /// alignment boundary. The size is guaranteed to be a multiple of the 516 /// stack alignment, and the alignment is guaranteed to be bigger than the 517 /// stack alignment (if required) or 0 to get standard stack alignment. 518 DYNAMIC_STACKALLOC, 519 520 /// Control flow instructions. These all have token chains. 521 522 /// BR - Unconditional branch. The first operand is the chain 523 /// operand, the second is the MBB to branch to. 524 BR, 525 526 /// BRIND - Indirect branch. The first operand is the chain, the second 527 /// is the value to branch to, which must be of the same type as the 528 /// target's pointer type. 529 BRIND, 530 531 /// BR_JT - Jumptable branch. The first operand is the chain, the second 532 /// is the jumptable index, the last one is the jumptable entry index. 533 BR_JT, 534 535 /// BRCOND - Conditional branch. The first operand is the chain, the 536 /// second is the condition, the third is the block to branch to if the 537 /// condition is true. If the type of the condition is not i1, then the 538 /// high bits must conform to getBooleanContents. 539 BRCOND, 540 541 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 542 /// that the condition is represented as condition code, and two nodes to 543 /// compare, rather than as a combined SetCC node. The operands in order 544 /// are chain, cc, lhs, rhs, block to branch to if condition is true. 545 BR_CC, 546 547 /// INLINEASM - Represents an inline asm block. This node always has two 548 /// return values: a chain and a flag result. The inputs are as follows: 549 /// Operand #0 : Input chain. 550 /// Operand #1 : a ExternalSymbolSDNode with a pointer to the asm string. 551 /// Operand #2 : a MDNodeSDNode with the !srcloc metadata. 552 /// Operand #3 : HasSideEffect, IsAlignStack bits. 553 /// After this, it is followed by a list of operands with this format: 554 /// ConstantSDNode: Flags that encode whether it is a mem or not, the 555 /// of operands that follow, etc. See InlineAsm.h. 556 /// ... however many operands ... 557 /// Operand #last: Optional, an incoming flag. 558 /// 559 /// The variable width operands are required to represent target addressing 560 /// modes as a single "operand", even though they may have multiple 561 /// SDOperands. 562 INLINEASM, 563 564 /// EH_LABEL - Represents a label in mid basic block used to track 565 /// locations needed for debug and exception handling tables. These nodes 566 /// take a chain as input and return a chain. 567 EH_LABEL, 568 569 /// STACKSAVE - STACKSAVE has one operand, an input chain. It produces a 570 /// value, the same type as the pointer type for the system, and an output 571 /// chain. 572 STACKSAVE, 573 574 /// STACKRESTORE has two operands, an input chain and a pointer to restore 575 /// to it returns an output chain. 576 STACKRESTORE, 577 578 /// CALLSEQ_START/CALLSEQ_END - These operators mark the beginning and end 579 /// of a call sequence, and carry arbitrary information that target might 580 /// want to know. The first operand is a chain, the rest are specified by 581 /// the target and not touched by the DAG optimizers. 582 /// CALLSEQ_START..CALLSEQ_END pairs may not be nested. 583 CALLSEQ_START, // Beginning of a call sequence 584 CALLSEQ_END, // End of a call sequence 585 586 /// VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, 587 /// and the alignment. It returns a pair of values: the vaarg value and a 588 /// new chain. 589 VAARG, 590 591 /// VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, 592 /// a source pointer, a SRCVALUE for the destination, and a SRCVALUE for the 593 /// source. 594 VACOPY, 595 596 /// VAEND, VASTART - VAEND and VASTART have three operands: an input chain, 597 /// pointer, and a SRCVALUE. 598 VAEND, VASTART, 599 600 /// SRCVALUE - This is a node type that holds a Value* that is used to 601 /// make reference to a value in the LLVM IR. 602 SRCVALUE, 603 604 /// MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to 605 /// reference metadata in the IR. 606 MDNODE_SDNODE, 607 608 /// PCMARKER - This corresponds to the pcmarker intrinsic. 609 PCMARKER, 610 611 /// READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic. 612 /// The only operand is a chain and a value and a chain are produced. The 613 /// value is the contents of the architecture specific cycle counter like 614 /// register (or other high accuracy low latency clock source) 615 READCYCLECOUNTER, 616 617 /// HANDLENODE node - Used as a handle for various purposes. 618 HANDLENODE, 619 620 /// INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic. It 621 /// takes as input a token chain, the pointer to the trampoline, the pointer 622 /// to the nested function, the pointer to pass for the 'nest' parameter, a 623 /// SRCVALUE for the trampoline and another for the nested function 624 /// (allowing targets to access the original Function*). 625 /// It produces a token chain as output. 626 INIT_TRAMPOLINE, 627 628 /// ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic. 629 /// It takes a pointer to the trampoline and produces a (possibly) new 630 /// pointer to the same trampoline with platform-specific adjustments 631 /// applied. The pointer it returns points to an executable block of code. 632 ADJUST_TRAMPOLINE, 633 634 /// TRAP - Trapping instruction 635 TRAP, 636 637 /// DEBUGTRAP - Trap intended to get the attention of a debugger. 638 DEBUGTRAP, 639 640 /// PREFETCH - This corresponds to a prefetch intrinsic. The first operand 641 /// is the chain. The other operands are the address to prefetch, 642 /// read / write specifier, locality specifier and instruction / data cache 643 /// specifier. 644 PREFETCH, 645 646 /// OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) 647 /// This corresponds to the fence instruction. It takes an input chain, and 648 /// two integer constants: an AtomicOrdering and a SynchronizationScope. 649 ATOMIC_FENCE, 650 651 /// Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) 652 /// This corresponds to "load atomic" instruction. 653 ATOMIC_LOAD, 654 655 /// OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) 656 /// This corresponds to "store atomic" instruction. 657 ATOMIC_STORE, 658 659 /// Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) 660 /// For double-word atomic operations: 661 /// ValLo, ValHi, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmpLo, cmpHi, 662 /// swapLo, swapHi) 663 /// This corresponds to the cmpxchg instruction. 664 ATOMIC_CMP_SWAP, 665 666 /// Val, Success, OUTCHAIN 667 /// = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) 668 /// N.b. this is still a strong cmpxchg operation, so 669 /// Success == "Val == cmp". 670 ATOMIC_CMP_SWAP_WITH_SUCCESS, 671 672 /// Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) 673 /// Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amt) 674 /// For double-word atomic operations: 675 /// ValLo, ValHi, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amtLo, amtHi) 676 /// ValLo, ValHi, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN, ptr, amtLo, amtHi) 677 /// These correspond to the atomicrmw instruction. 678 ATOMIC_SWAP, 679 ATOMIC_LOAD_ADD, 680 ATOMIC_LOAD_SUB, 681 ATOMIC_LOAD_AND, 682 ATOMIC_LOAD_OR, 683 ATOMIC_LOAD_XOR, 684 ATOMIC_LOAD_NAND, 685 ATOMIC_LOAD_MIN, 686 ATOMIC_LOAD_MAX, 687 ATOMIC_LOAD_UMIN, 688 ATOMIC_LOAD_UMAX, 689 690 // Masked load and store 691 MLOAD, MSTORE, 692 693 /// This corresponds to the llvm.lifetime.* intrinsics. The first operand 694 /// is the chain and the second operand is the alloca pointer. 695 LIFETIME_START, LIFETIME_END, 696 697 /// BUILTIN_OP_END - This must be the last enum value in this list. 698 /// The target-specific pre-isel opcode values start here. 699 BUILTIN_OP_END 700 }; 701 702 /// FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations 703 /// which do not reference a specific memory location should be less than 704 /// this value. Those that do must not be less than this value, and can 705 /// be used with SelectionDAG::getMemIntrinsicNode. 706 static const int FIRST_TARGET_MEMORY_OPCODE = BUILTIN_OP_END+200; 707 708 //===--------------------------------------------------------------------===// 709 /// MemIndexedMode enum - This enum defines the load / store indexed 710 /// addressing modes. 711 /// 712 /// UNINDEXED "Normal" load / store. The effective address is already 713 /// computed and is available in the base pointer. The offset 714 /// operand is always undefined. In addition to producing a 715 /// chain, an unindexed load produces one value (result of the 716 /// load); an unindexed store does not produce a value. 717 /// 718 /// PRE_INC Similar to the unindexed mode where the effective address is 719 /// PRE_DEC the value of the base pointer add / subtract the offset. 720 /// It considers the computation as being folded into the load / 721 /// store operation (i.e. the load / store does the address 722 /// computation as well as performing the memory transaction). 723 /// The base operand is always undefined. In addition to 724 /// producing a chain, pre-indexed load produces two values 725 /// (result of the load and the result of the address 726 /// computation); a pre-indexed store produces one value (result 727 /// of the address computation). 728 /// 729 /// POST_INC The effective address is the value of the base pointer. The 730 /// POST_DEC value of the offset operand is then added to / subtracted 731 /// from the base after memory transaction. In addition to 732 /// producing a chain, post-indexed load produces two values 733 /// (the result of the load and the result of the base +/- offset 734 /// computation); a post-indexed store produces one value (the 735 /// the result of the base +/- offset computation). 736 enum MemIndexedMode { 737 UNINDEXED = 0, 738 PRE_INC, 739 PRE_DEC, 740 POST_INC, 741 POST_DEC, 742 LAST_INDEXED_MODE 743 }; 744 745 //===--------------------------------------------------------------------===// 746 /// LoadExtType enum - This enum defines the three variants of LOADEXT 747 /// (load with extension). 748 /// 749 /// SEXTLOAD loads the integer operand and sign extends it to a larger 750 /// integer result type. 751 /// ZEXTLOAD loads the integer operand and zero extends it to a larger 752 /// integer result type. 753 /// EXTLOAD is used for two things: floating point extending loads and 754 /// integer extending loads [the top bits are undefined]. 755 enum LoadExtType { 756 NON_EXTLOAD = 0, 757 EXTLOAD, 758 SEXTLOAD, 759 ZEXTLOAD, 760 LAST_LOADEXT_TYPE 761 }; 762 763 NodeType getExtForLoadExtType(bool IsFP, LoadExtType); 764 765 //===--------------------------------------------------------------------===// 766 /// ISD::CondCode enum - These are ordered carefully to make the bitfields 767 /// below work out, when considering SETFALSE (something that never exists 768 /// dynamically) as 0. "U" -> Unsigned (for integer operands) or Unordered 769 /// (for floating point), "L" -> Less than, "G" -> Greater than, "E" -> Equal 770 /// to. If the "N" column is 1, the result of the comparison is undefined if 771 /// the input is a NAN. 772 /// 773 /// All of these (except for the 'always folded ops') should be handled for 774 /// floating point. For integer, only the SETEQ,SETNE,SETLT,SETLE,SETGT, 775 /// SETGE,SETULT,SETULE,SETUGT, and SETUGE opcodes are used. 776 /// 777 /// Note that these are laid out in a specific order to allow bit-twiddling 778 /// to transform conditions. 779 enum CondCode { 780 // Opcode N U L G E Intuitive operation 781 SETFALSE, // 0 0 0 0 Always false (always folded) 782 SETOEQ, // 0 0 0 1 True if ordered and equal 783 SETOGT, // 0 0 1 0 True if ordered and greater than 784 SETOGE, // 0 0 1 1 True if ordered and greater than or equal 785 SETOLT, // 0 1 0 0 True if ordered and less than 786 SETOLE, // 0 1 0 1 True if ordered and less than or equal 787 SETONE, // 0 1 1 0 True if ordered and operands are unequal 788 SETO, // 0 1 1 1 True if ordered (no nans) 789 SETUO, // 1 0 0 0 True if unordered: isnan(X) | isnan(Y) 790 SETUEQ, // 1 0 0 1 True if unordered or equal 791 SETUGT, // 1 0 1 0 True if unordered or greater than 792 SETUGE, // 1 0 1 1 True if unordered, greater than, or equal 793 SETULT, // 1 1 0 0 True if unordered or less than 794 SETULE, // 1 1 0 1 True if unordered, less than, or equal 795 SETUNE, // 1 1 1 0 True if unordered or not equal 796 SETTRUE, // 1 1 1 1 Always true (always folded) 797 // Don't care operations: undefined if the input is a nan. 798 SETFALSE2, // 1 X 0 0 0 Always false (always folded) 799 SETEQ, // 1 X 0 0 1 True if equal 800 SETGT, // 1 X 0 1 0 True if greater than 801 SETGE, // 1 X 0 1 1 True if greater than or equal 802 SETLT, // 1 X 1 0 0 True if less than 803 SETLE, // 1 X 1 0 1 True if less than or equal 804 SETNE, // 1 X 1 1 0 True if not equal 805 SETTRUE2, // 1 X 1 1 1 Always true (always folded) 806 807 SETCC_INVALID // Marker value. 808 }; 809 810 /// isSignedIntSetCC - Return true if this is a setcc instruction that 811 /// performs a signed comparison when used with integer operands. isSignedIntSetCC(CondCode Code)812 inline bool isSignedIntSetCC(CondCode Code) { 813 return Code == SETGT || Code == SETGE || Code == SETLT || Code == SETLE; 814 } 815 816 /// isUnsignedIntSetCC - Return true if this is a setcc instruction that 817 /// performs an unsigned comparison when used with integer operands. isUnsignedIntSetCC(CondCode Code)818 inline bool isUnsignedIntSetCC(CondCode Code) { 819 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; 820 } 821 822 /// isTrueWhenEqual - Return true if the specified condition returns true if 823 /// the two operands to the condition are equal. Note that if one of the two 824 /// operands is a NaN, this value is meaningless. isTrueWhenEqual(CondCode Cond)825 inline bool isTrueWhenEqual(CondCode Cond) { 826 return ((int)Cond & 1) != 0; 827 } 828 829 /// getUnorderedFlavor - This function returns 0 if the condition is always 830 /// false if an operand is a NaN, 1 if the condition is always true if the 831 /// operand is a NaN, and 2 if the condition is undefined if the operand is a 832 /// NaN. getUnorderedFlavor(CondCode Cond)833 inline unsigned getUnorderedFlavor(CondCode Cond) { 834 return ((int)Cond >> 3) & 3; 835 } 836 837 /// getSetCCInverse - Return the operation corresponding to !(X op Y), where 838 /// 'op' is a valid SetCC operation. 839 CondCode getSetCCInverse(CondCode Operation, bool isInteger); 840 841 /// getSetCCSwappedOperands - Return the operation corresponding to (Y op X) 842 /// when given the operation for (X op Y). 843 CondCode getSetCCSwappedOperands(CondCode Operation); 844 845 /// getSetCCOrOperation - Return the result of a logical OR between different 846 /// comparisons of identical values: ((X op1 Y) | (X op2 Y)). This 847 /// function returns SETCC_INVALID if it is not possible to represent the 848 /// resultant comparison. 849 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger); 850 851 /// getSetCCAndOperation - Return the result of a logical AND between 852 /// different comparisons of identical values: ((X op1 Y) & (X op2 Y)). This 853 /// function returns SETCC_INVALID if it is not possible to represent the 854 /// resultant comparison. 855 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger); 856 857 //===--------------------------------------------------------------------===// 858 /// CvtCode enum - This enum defines the various converts CONVERT_RNDSAT 859 /// supports. 860 enum CvtCode { 861 CVT_FF, /// Float from Float 862 CVT_FS, /// Float from Signed 863 CVT_FU, /// Float from Unsigned 864 CVT_SF, /// Signed from Float 865 CVT_UF, /// Unsigned from Float 866 CVT_SS, /// Signed from Signed 867 CVT_SU, /// Signed from Unsigned 868 CVT_US, /// Unsigned from Signed 869 CVT_UU, /// Unsigned from Unsigned 870 CVT_INVALID /// Marker - Invalid opcode 871 }; 872 873 } // end llvm::ISD namespace 874 875 } // end llvm namespace 876 877 #endif 878