1 //===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file is part of the Mips Disassembler.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "Mips.h"
15 #include "MipsRegisterInfo.h"
16 #include "MipsSubtarget.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCDisassembler.h"
19 #include "llvm/MC/MCFixedLenDisassembler.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/MathExtras.h"
23 #include "llvm/Support/TargetRegistry.h"
24
25 using namespace llvm;
26
27 #define DEBUG_TYPE "mips-disassembler"
28
29 typedef MCDisassembler::DecodeStatus DecodeStatus;
30
31 namespace {
32
33 class MipsDisassembler : public MCDisassembler {
34 bool IsMicroMips;
35 bool IsBigEndian;
36 public:
MipsDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx,bool IsBigEndian)37 MipsDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, bool IsBigEndian)
38 : MCDisassembler(STI, Ctx),
39 IsMicroMips(STI.getFeatureBits() & Mips::FeatureMicroMips),
40 IsBigEndian(IsBigEndian) {}
41
hasMips3() const42 bool hasMips3() const { return STI.getFeatureBits() & Mips::FeatureMips3; }
hasMips32() const43 bool hasMips32() const { return STI.getFeatureBits() & Mips::FeatureMips32; }
hasMips32r6() const44 bool hasMips32r6() const {
45 return STI.getFeatureBits() & Mips::FeatureMips32r6;
46 }
47
isGP64() const48 bool isGP64() const { return STI.getFeatureBits() & Mips::FeatureGP64Bit; }
49
hasCOP3() const50 bool hasCOP3() const {
51 // Only present in MIPS-I and MIPS-II
52 return !hasMips32() && !hasMips3();
53 }
54
55 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
56 ArrayRef<uint8_t> Bytes, uint64_t Address,
57 raw_ostream &VStream,
58 raw_ostream &CStream) const override;
59 };
60
61 } // end anonymous namespace
62
63 // Forward declare these because the autogenerated code will reference them.
64 // Definitions are further down.
65 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
66 unsigned RegNo,
67 uint64_t Address,
68 const void *Decoder);
69
70 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
71 unsigned RegNo,
72 uint64_t Address,
73 const void *Decoder);
74
75 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
76 unsigned RegNo,
77 uint64_t Address,
78 const void *Decoder);
79
80 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
81 unsigned RegNo,
82 uint64_t Address,
83 const void *Decoder);
84
85 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
86 unsigned RegNo,
87 uint64_t Address,
88 const void *Decoder);
89
90 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
91 unsigned RegNo,
92 uint64_t Address,
93 const void *Decoder);
94
95 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
96 unsigned Insn,
97 uint64_t Address,
98 const void *Decoder);
99
100 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
101 unsigned RegNo,
102 uint64_t Address,
103 const void *Decoder);
104
105 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
106 unsigned RegNo,
107 uint64_t Address,
108 const void *Decoder);
109
110 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
111 unsigned RegNo,
112 uint64_t Address,
113 const void *Decoder);
114
115 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
116 unsigned RegNo,
117 uint64_t Address,
118 const void *Decoder);
119
120 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
121 unsigned RegNo,
122 uint64_t Address,
123 const void *Decoder);
124
125 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
126 uint64_t Address,
127 const void *Decoder);
128
129 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
130 unsigned Insn,
131 uint64_t Address,
132 const void *Decoder);
133
134 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
135 unsigned RegNo,
136 uint64_t Address,
137 const void *Decoder);
138
139 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
140 unsigned RegNo,
141 uint64_t Address,
142 const void *Decoder);
143
144 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
145 unsigned RegNo,
146 uint64_t Address,
147 const void *Decoder);
148
149 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
150 unsigned RegNo,
151 uint64_t Address,
152 const void *Decoder);
153
154 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
155 unsigned RegNo,
156 uint64_t Address,
157 const void *Decoder);
158
159 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
160 unsigned RegNo,
161 uint64_t Address,
162 const void *Decoder);
163
164 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
165 unsigned RegNo,
166 uint64_t Address,
167 const void *Decoder);
168
169 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
170 unsigned RegNo,
171 uint64_t Address,
172 const void *Decoder);
173
174 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
175 unsigned RegNo,
176 uint64_t Address,
177 const void *Decoder);
178
179 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
180 unsigned RegNo,
181 uint64_t Address,
182 const void *Decoder);
183
184 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
185 unsigned Offset,
186 uint64_t Address,
187 const void *Decoder);
188
189 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
190 unsigned Insn,
191 uint64_t Address,
192 const void *Decoder);
193
194 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
195 unsigned Offset,
196 uint64_t Address,
197 const void *Decoder);
198
199 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
200 unsigned Offset,
201 uint64_t Address,
202 const void *Decoder);
203
204 // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is
205 // shifted left by 1 bit.
206 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
207 unsigned Offset,
208 uint64_t Address,
209 const void *Decoder);
210
211 // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is
212 // shifted left by 1 bit.
213 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
214 unsigned Offset,
215 uint64_t Address,
216 const void *Decoder);
217
218 // DecodeBranchTargetMM - Decode microMIPS branch offset, which is
219 // shifted left by 1 bit.
220 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
221 unsigned Offset,
222 uint64_t Address,
223 const void *Decoder);
224
225 // DecodeJumpTargetMM - Decode microMIPS jump target, which is
226 // shifted left by 1 bit.
227 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
228 unsigned Insn,
229 uint64_t Address,
230 const void *Decoder);
231
232 static DecodeStatus DecodeMem(MCInst &Inst,
233 unsigned Insn,
234 uint64_t Address,
235 const void *Decoder);
236
237 static DecodeStatus DecodeCacheOp(MCInst &Inst,
238 unsigned Insn,
239 uint64_t Address,
240 const void *Decoder);
241
242 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
243 unsigned Insn,
244 uint64_t Address,
245 const void *Decoder);
246
247 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
248 unsigned Insn,
249 uint64_t Address,
250 const void *Decoder);
251
252 static DecodeStatus DecodeSyncI(MCInst &Inst,
253 unsigned Insn,
254 uint64_t Address,
255 const void *Decoder);
256
257 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
258 uint64_t Address, const void *Decoder);
259
260 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
261 unsigned Insn,
262 uint64_t Address,
263 const void *Decoder);
264
265 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
266 unsigned Insn,
267 uint64_t Address,
268 const void *Decoder);
269
270 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
271 unsigned Insn,
272 uint64_t Address,
273 const void *Decoder);
274
275 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
276 unsigned Insn,
277 uint64_t Address,
278 const void *Decoder);
279
280 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
281 unsigned Insn,
282 uint64_t Address,
283 const void *Decoder);
284
285 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
286 unsigned Insn,
287 uint64_t Address,
288 const void *Decoder);
289
290 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
291 uint64_t Address,
292 const void *Decoder);
293
294 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn,
295 uint64_t Address,
296 const void *Decoder);
297
298 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn,
299 uint64_t Address,
300 const void *Decoder);
301
302 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
303 uint64_t Address,
304 const void *Decoder);
305
306 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
307 unsigned Insn,
308 uint64_t Address,
309 const void *Decoder);
310
311 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
312 unsigned Value,
313 uint64_t Address,
314 const void *Decoder);
315
316 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
317 unsigned Value,
318 uint64_t Address,
319 const void *Decoder);
320
321 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
322 unsigned Value,
323 uint64_t Address,
324 const void *Decoder);
325
326 static DecodeStatus DecodeSimm4(MCInst &Inst,
327 unsigned Value,
328 uint64_t Address,
329 const void *Decoder);
330
331 static DecodeStatus DecodeSimm16(MCInst &Inst,
332 unsigned Insn,
333 uint64_t Address,
334 const void *Decoder);
335
336 // Decode the immediate field of an LSA instruction which
337 // is off by one.
338 static DecodeStatus DecodeLSAImm(MCInst &Inst,
339 unsigned Insn,
340 uint64_t Address,
341 const void *Decoder);
342
343 static DecodeStatus DecodeInsSize(MCInst &Inst,
344 unsigned Insn,
345 uint64_t Address,
346 const void *Decoder);
347
348 static DecodeStatus DecodeExtSize(MCInst &Inst,
349 unsigned Insn,
350 uint64_t Address,
351 const void *Decoder);
352
353 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
354 uint64_t Address, const void *Decoder);
355
356 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
357 uint64_t Address, const void *Decoder);
358
359 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
360 uint64_t Address, const void *Decoder);
361
362 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
363 uint64_t Address, const void *Decoder);
364
365 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
366 uint64_t Address, const void *Decoder);
367
368 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
369 uint64_t Address, const void *Decoder);
370
371 /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't
372 /// handle.
373 template <typename InsnType>
374 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
375 const void *Decoder);
376
377 template <typename InsnType>
378 static DecodeStatus
379 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
380 const void *Decoder);
381
382 template <typename InsnType>
383 static DecodeStatus
384 DecodeDaddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
385 const void *Decoder);
386
387 template <typename InsnType>
388 static DecodeStatus
389 DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
390 const void *Decoder);
391
392 template <typename InsnType>
393 static DecodeStatus
394 DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
395 const void *Decoder);
396
397 template <typename InsnType>
398 static DecodeStatus
399 DecodeBgtzGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
400 const void *Decoder);
401
402 template <typename InsnType>
403 static DecodeStatus
404 DecodeBlezGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
405 const void *Decoder);
406
407 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
408 uint64_t Address,
409 const void *Decoder);
410
411 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
412 uint64_t Address,
413 const void *Decoder);
414
415 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
416 uint64_t Address,
417 const void *Decoder);
418
419 namespace llvm {
420 extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
421 TheMips64elTarget;
422 }
423
createMipsDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)424 static MCDisassembler *createMipsDisassembler(
425 const Target &T,
426 const MCSubtargetInfo &STI,
427 MCContext &Ctx) {
428 return new MipsDisassembler(STI, Ctx, true);
429 }
430
createMipselDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)431 static MCDisassembler *createMipselDisassembler(
432 const Target &T,
433 const MCSubtargetInfo &STI,
434 MCContext &Ctx) {
435 return new MipsDisassembler(STI, Ctx, false);
436 }
437
LLVMInitializeMipsDisassembler()438 extern "C" void LLVMInitializeMipsDisassembler() {
439 // Register the disassembler.
440 TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
441 createMipsDisassembler);
442 TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
443 createMipselDisassembler);
444 TargetRegistry::RegisterMCDisassembler(TheMips64Target,
445 createMipsDisassembler);
446 TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
447 createMipselDisassembler);
448 }
449
450 #include "MipsGenDisassemblerTables.inc"
451
getReg(const void * D,unsigned RC,unsigned RegNo)452 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
453 const MipsDisassembler *Dis = static_cast<const MipsDisassembler*>(D);
454 const MCRegisterInfo *RegInfo = Dis->getContext().getRegisterInfo();
455 return *(RegInfo->getRegClass(RC).begin() + RegNo);
456 }
457
458 template <typename InsnType>
DecodeINSVE_DF(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)459 static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address,
460 const void *Decoder) {
461 typedef DecodeStatus (*DecodeFN)(MCInst &, unsigned, uint64_t, const void *);
462 // The size of the n field depends on the element size
463 // The register class also depends on this.
464 InsnType tmp = fieldFromInstruction(insn, 17, 5);
465 unsigned NSize = 0;
466 DecodeFN RegDecoder = nullptr;
467 if ((tmp & 0x18) == 0x00) { // INSVE_B
468 NSize = 4;
469 RegDecoder = DecodeMSA128BRegisterClass;
470 } else if ((tmp & 0x1c) == 0x10) { // INSVE_H
471 NSize = 3;
472 RegDecoder = DecodeMSA128HRegisterClass;
473 } else if ((tmp & 0x1e) == 0x18) { // INSVE_W
474 NSize = 2;
475 RegDecoder = DecodeMSA128WRegisterClass;
476 } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D
477 NSize = 1;
478 RegDecoder = DecodeMSA128DRegisterClass;
479 } else
480 llvm_unreachable("Invalid encoding");
481
482 assert(NSize != 0 && RegDecoder != nullptr);
483
484 // $wd
485 tmp = fieldFromInstruction(insn, 6, 5);
486 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
487 return MCDisassembler::Fail;
488 // $wd_in
489 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
490 return MCDisassembler::Fail;
491 // $n
492 tmp = fieldFromInstruction(insn, 16, NSize);
493 MI.addOperand(MCOperand::CreateImm(tmp));
494 // $ws
495 tmp = fieldFromInstruction(insn, 11, 5);
496 if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler::Fail)
497 return MCDisassembler::Fail;
498 // $n2
499 MI.addOperand(MCOperand::CreateImm(0));
500
501 return MCDisassembler::Success;
502 }
503
504 template <typename InsnType>
DecodeAddiGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)505 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
506 uint64_t Address,
507 const void *Decoder) {
508 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
509 // (otherwise we would have matched the ADDI instruction from the earlier
510 // ISA's instead).
511 //
512 // We have:
513 // 0b001000 sssss ttttt iiiiiiiiiiiiiiii
514 // BOVC if rs >= rt
515 // BEQZALC if rs == 0 && rt != 0
516 // BEQC if rs < rt && rs != 0
517
518 InsnType Rs = fieldFromInstruction(insn, 21, 5);
519 InsnType Rt = fieldFromInstruction(insn, 16, 5);
520 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
521 bool HasRs = false;
522
523 if (Rs >= Rt) {
524 MI.setOpcode(Mips::BOVC);
525 HasRs = true;
526 } else if (Rs != 0 && Rs < Rt) {
527 MI.setOpcode(Mips::BEQC);
528 HasRs = true;
529 } else
530 MI.setOpcode(Mips::BEQZALC);
531
532 if (HasRs)
533 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
534 Rs)));
535
536 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
537 Rt)));
538 MI.addOperand(MCOperand::CreateImm(Imm));
539
540 return MCDisassembler::Success;
541 }
542
543 template <typename InsnType>
DecodeDaddiGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)544 static DecodeStatus DecodeDaddiGroupBranch(MCInst &MI, InsnType insn,
545 uint64_t Address,
546 const void *Decoder) {
547 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
548 // (otherwise we would have matched the ADDI instruction from the earlier
549 // ISA's instead).
550 //
551 // We have:
552 // 0b011000 sssss ttttt iiiiiiiiiiiiiiii
553 // BNVC if rs >= rt
554 // BNEZALC if rs == 0 && rt != 0
555 // BNEC if rs < rt && rs != 0
556
557 InsnType Rs = fieldFromInstruction(insn, 21, 5);
558 InsnType Rt = fieldFromInstruction(insn, 16, 5);
559 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
560 bool HasRs = false;
561
562 if (Rs >= Rt) {
563 MI.setOpcode(Mips::BNVC);
564 HasRs = true;
565 } else if (Rs != 0 && Rs < Rt) {
566 MI.setOpcode(Mips::BNEC);
567 HasRs = true;
568 } else
569 MI.setOpcode(Mips::BNEZALC);
570
571 if (HasRs)
572 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
573 Rs)));
574
575 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
576 Rt)));
577 MI.addOperand(MCOperand::CreateImm(Imm));
578
579 return MCDisassembler::Success;
580 }
581
582 template <typename InsnType>
DecodeBlezlGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)583 static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn,
584 uint64_t Address,
585 const void *Decoder) {
586 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
587 // (otherwise we would have matched the BLEZL instruction from the earlier
588 // ISA's instead).
589 //
590 // We have:
591 // 0b010110 sssss ttttt iiiiiiiiiiiiiiii
592 // Invalid if rs == 0
593 // BLEZC if rs == 0 && rt != 0
594 // BGEZC if rs == rt && rt != 0
595 // BGEC if rs != rt && rs != 0 && rt != 0
596
597 InsnType Rs = fieldFromInstruction(insn, 21, 5);
598 InsnType Rt = fieldFromInstruction(insn, 16, 5);
599 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
600 bool HasRs = false;
601
602 if (Rt == 0)
603 return MCDisassembler::Fail;
604 else if (Rs == 0)
605 MI.setOpcode(Mips::BLEZC);
606 else if (Rs == Rt)
607 MI.setOpcode(Mips::BGEZC);
608 else {
609 HasRs = true;
610 MI.setOpcode(Mips::BGEC);
611 }
612
613 if (HasRs)
614 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
615 Rs)));
616
617 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
618 Rt)));
619
620 MI.addOperand(MCOperand::CreateImm(Imm));
621
622 return MCDisassembler::Success;
623 }
624
625 template <typename InsnType>
DecodeBgtzlGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)626 static DecodeStatus DecodeBgtzlGroupBranch(MCInst &MI, InsnType insn,
627 uint64_t Address,
628 const void *Decoder) {
629 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
630 // (otherwise we would have matched the BGTZL instruction from the earlier
631 // ISA's instead).
632 //
633 // We have:
634 // 0b010111 sssss ttttt iiiiiiiiiiiiiiii
635 // Invalid if rs == 0
636 // BGTZC if rs == 0 && rt != 0
637 // BLTZC if rs == rt && rt != 0
638 // BLTC if rs != rt && rs != 0 && rt != 0
639
640 bool HasRs = false;
641
642 InsnType Rs = fieldFromInstruction(insn, 21, 5);
643 InsnType Rt = fieldFromInstruction(insn, 16, 5);
644 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
645
646 if (Rt == 0)
647 return MCDisassembler::Fail;
648 else if (Rs == 0)
649 MI.setOpcode(Mips::BGTZC);
650 else if (Rs == Rt)
651 MI.setOpcode(Mips::BLTZC);
652 else {
653 MI.setOpcode(Mips::BLTC);
654 HasRs = true;
655 }
656
657 if (HasRs)
658 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
659 Rs)));
660
661 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
662 Rt)));
663
664 MI.addOperand(MCOperand::CreateImm(Imm));
665
666 return MCDisassembler::Success;
667 }
668
669 template <typename InsnType>
DecodeBgtzGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)670 static DecodeStatus DecodeBgtzGroupBranch(MCInst &MI, InsnType insn,
671 uint64_t Address,
672 const void *Decoder) {
673 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
674 // (otherwise we would have matched the BGTZ instruction from the earlier
675 // ISA's instead).
676 //
677 // We have:
678 // 0b000111 sssss ttttt iiiiiiiiiiiiiiii
679 // BGTZ if rt == 0
680 // BGTZALC if rs == 0 && rt != 0
681 // BLTZALC if rs != 0 && rs == rt
682 // BLTUC if rs != 0 && rs != rt
683
684 InsnType Rs = fieldFromInstruction(insn, 21, 5);
685 InsnType Rt = fieldFromInstruction(insn, 16, 5);
686 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
687 bool HasRs = false;
688 bool HasRt = false;
689
690 if (Rt == 0) {
691 MI.setOpcode(Mips::BGTZ);
692 HasRs = true;
693 } else if (Rs == 0) {
694 MI.setOpcode(Mips::BGTZALC);
695 HasRt = true;
696 } else if (Rs == Rt) {
697 MI.setOpcode(Mips::BLTZALC);
698 HasRs = true;
699 } else {
700 MI.setOpcode(Mips::BLTUC);
701 HasRs = true;
702 HasRt = true;
703 }
704
705 if (HasRs)
706 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
707 Rs)));
708
709 if (HasRt)
710 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
711 Rt)));
712
713 MI.addOperand(MCOperand::CreateImm(Imm));
714
715 return MCDisassembler::Success;
716 }
717
718 template <typename InsnType>
DecodeBlezGroupBranch(MCInst & MI,InsnType insn,uint64_t Address,const void * Decoder)719 static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn,
720 uint64_t Address,
721 const void *Decoder) {
722 // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled
723 // (otherwise we would have matched the BLEZL instruction from the earlier
724 // ISA's instead).
725 //
726 // We have:
727 // 0b000110 sssss ttttt iiiiiiiiiiiiiiii
728 // Invalid if rs == 0
729 // BLEZALC if rs == 0 && rt != 0
730 // BGEZALC if rs == rt && rt != 0
731 // BGEUC if rs != rt && rs != 0 && rt != 0
732
733 InsnType Rs = fieldFromInstruction(insn, 21, 5);
734 InsnType Rt = fieldFromInstruction(insn, 16, 5);
735 InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4;
736 bool HasRs = false;
737
738 if (Rt == 0)
739 return MCDisassembler::Fail;
740 else if (Rs == 0)
741 MI.setOpcode(Mips::BLEZALC);
742 else if (Rs == Rt)
743 MI.setOpcode(Mips::BGEZALC);
744 else {
745 HasRs = true;
746 MI.setOpcode(Mips::BGEUC);
747 }
748
749 if (HasRs)
750 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
751 Rs)));
752 MI.addOperand(MCOperand::CreateReg(getReg(Decoder, Mips::GPR32RegClassID,
753 Rt)));
754
755 MI.addOperand(MCOperand::CreateImm(Imm));
756
757 return MCDisassembler::Success;
758 }
759
760 /// Read two bytes from the ArrayRef and return 16 bit halfword sorted
761 /// according to the given endianess.
readInstruction16(ArrayRef<uint8_t> Bytes,uint64_t Address,uint64_t & Size,uint32_t & Insn,bool IsBigEndian)762 static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
763 uint64_t &Size, uint32_t &Insn,
764 bool IsBigEndian) {
765 // We want to read exactly 2 Bytes of data.
766 if (Bytes.size() < 2) {
767 Size = 0;
768 return MCDisassembler::Fail;
769 }
770
771 if (IsBigEndian) {
772 Insn = (Bytes[0] << 8) | Bytes[1];
773 } else {
774 Insn = (Bytes[1] << 8) | Bytes[0];
775 }
776
777 return MCDisassembler::Success;
778 }
779
780 /// Read four bytes from the ArrayRef and return 32 bit word sorted
781 /// according to the given endianess
readInstruction32(ArrayRef<uint8_t> Bytes,uint64_t Address,uint64_t & Size,uint32_t & Insn,bool IsBigEndian,bool IsMicroMips)782 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
783 uint64_t &Size, uint32_t &Insn,
784 bool IsBigEndian, bool IsMicroMips) {
785 // We want to read exactly 4 Bytes of data.
786 if (Bytes.size() < 4) {
787 Size = 0;
788 return MCDisassembler::Fail;
789 }
790
791 // High 16 bits of a 32-bit microMIPS instruction (where the opcode is)
792 // always precede the low 16 bits in the instruction stream (that is, they
793 // are placed at lower addresses in the instruction stream).
794 //
795 // microMIPS byte ordering:
796 // Big-endian: 0 | 1 | 2 | 3
797 // Little-endian: 1 | 0 | 3 | 2
798
799 if (IsBigEndian) {
800 // Encoded as a big-endian 32-bit word in the stream.
801 Insn =
802 (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | (Bytes[0] << 24);
803 } else {
804 if (IsMicroMips) {
805 Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | (Bytes[0] << 16) |
806 (Bytes[1] << 24);
807 } else {
808 Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
809 (Bytes[3] << 24);
810 }
811 }
812
813 return MCDisassembler::Success;
814 }
815
getInstruction(MCInst & Instr,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & VStream,raw_ostream & CStream) const816 DecodeStatus MipsDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
817 ArrayRef<uint8_t> Bytes,
818 uint64_t Address,
819 raw_ostream &VStream,
820 raw_ostream &CStream) const {
821 uint32_t Insn;
822 DecodeStatus Result;
823
824 if (IsMicroMips) {
825 Result = readInstruction16(Bytes, Address, Size, Insn, IsBigEndian);
826
827 DEBUG(dbgs() << "Trying MicroMips16 table (16-bit instructions):\n");
828 // Calling the auto-generated decoder function.
829 Result = decodeInstruction(DecoderTableMicroMips16, Instr, Insn, Address,
830 this, STI);
831 if (Result != MCDisassembler::Fail) {
832 Size = 2;
833 return Result;
834 }
835
836 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, true);
837 if (Result == MCDisassembler::Fail)
838 return MCDisassembler::Fail;
839
840 DEBUG(dbgs() << "Trying MicroMips32 table (32-bit instructions):\n");
841 // Calling the auto-generated decoder function.
842 Result = decodeInstruction(DecoderTableMicroMips32, Instr, Insn, Address,
843 this, STI);
844 if (Result != MCDisassembler::Fail) {
845 Size = 4;
846 return Result;
847 }
848 return MCDisassembler::Fail;
849 }
850
851 Result = readInstruction32(Bytes, Address, Size, Insn, IsBigEndian, false);
852 if (Result == MCDisassembler::Fail)
853 return MCDisassembler::Fail;
854
855 if (hasCOP3()) {
856 DEBUG(dbgs() << "Trying COP3_ table (32-bit opcodes):\n");
857 Result =
858 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
859 if (Result != MCDisassembler::Fail) {
860 Size = 4;
861 return Result;
862 }
863 }
864
865 if (hasMips32r6() && isGP64()) {
866 DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
867 Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, Instr, Insn,
868 Address, this, STI);
869 if (Result != MCDisassembler::Fail) {
870 Size = 4;
871 return Result;
872 }
873 }
874
875 if (hasMips32r6()) {
876 DEBUG(dbgs() << "Trying Mips32r6_64r6 table (32-bit opcodes):\n");
877 Result = decodeInstruction(DecoderTableMips32r6_64r632, Instr, Insn,
878 Address, this, STI);
879 if (Result != MCDisassembler::Fail) {
880 Size = 4;
881 return Result;
882 }
883 }
884
885 if (isGP64()) {
886 DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
887 Result = decodeInstruction(DecoderTableMips6432, Instr, Insn,
888 Address, this, STI);
889 if (Result != MCDisassembler::Fail) {
890 Size = 4;
891 return Result;
892 }
893 }
894
895 DEBUG(dbgs() << "Trying Mips table (32-bit opcodes):\n");
896 // Calling the auto-generated decoder function.
897 Result =
898 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
899 if (Result != MCDisassembler::Fail) {
900 Size = 4;
901 return Result;
902 }
903
904 return MCDisassembler::Fail;
905 }
906
DecodeCPU16RegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)907 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
908 unsigned RegNo,
909 uint64_t Address,
910 const void *Decoder) {
911
912 return MCDisassembler::Fail;
913
914 }
915
DecodeGPR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)916 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
917 unsigned RegNo,
918 uint64_t Address,
919 const void *Decoder) {
920
921 if (RegNo > 31)
922 return MCDisassembler::Fail;
923
924 unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
925 Inst.addOperand(MCOperand::CreateReg(Reg));
926 return MCDisassembler::Success;
927 }
928
DecodeGPRMM16RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)929 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
930 unsigned RegNo,
931 uint64_t Address,
932 const void *Decoder) {
933 if (RegNo > 7)
934 return MCDisassembler::Fail;
935 unsigned Reg = getReg(Decoder, Mips::GPRMM16RegClassID, RegNo);
936 Inst.addOperand(MCOperand::CreateReg(Reg));
937 return MCDisassembler::Success;
938 }
939
DecodeGPRMM16ZeroRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)940 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
941 unsigned RegNo,
942 uint64_t Address,
943 const void *Decoder) {
944 if (RegNo > 7)
945 return MCDisassembler::Fail;
946 unsigned Reg = getReg(Decoder, Mips::GPRMM16ZeroRegClassID, RegNo);
947 Inst.addOperand(MCOperand::CreateReg(Reg));
948 return MCDisassembler::Success;
949 }
950
DecodeGPRMM16MovePRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)951 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
952 unsigned RegNo,
953 uint64_t Address,
954 const void *Decoder) {
955 if (RegNo > 7)
956 return MCDisassembler::Fail;
957 unsigned Reg = getReg(Decoder, Mips::GPRMM16MovePRegClassID, RegNo);
958 Inst.addOperand(MCOperand::CreateReg(Reg));
959 return MCDisassembler::Success;
960 }
961
DecodeGPR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)962 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
963 unsigned RegNo,
964 uint64_t Address,
965 const void *Decoder) {
966 if (RegNo > 31)
967 return MCDisassembler::Fail;
968 unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
969 Inst.addOperand(MCOperand::CreateReg(Reg));
970 return MCDisassembler::Success;
971 }
972
DecodePtrRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)973 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
974 unsigned RegNo,
975 uint64_t Address,
976 const void *Decoder) {
977 if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
978 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
979
980 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
981 }
982
DecodeDSPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)983 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
984 unsigned RegNo,
985 uint64_t Address,
986 const void *Decoder) {
987 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
988 }
989
DecodeFGR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)990 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
991 unsigned RegNo,
992 uint64_t Address,
993 const void *Decoder) {
994 if (RegNo > 31)
995 return MCDisassembler::Fail;
996
997 unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
998 Inst.addOperand(MCOperand::CreateReg(Reg));
999 return MCDisassembler::Success;
1000 }
1001
DecodeFGR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1002 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
1003 unsigned RegNo,
1004 uint64_t Address,
1005 const void *Decoder) {
1006 if (RegNo > 31)
1007 return MCDisassembler::Fail;
1008
1009 unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
1010 Inst.addOperand(MCOperand::CreateReg(Reg));
1011 return MCDisassembler::Success;
1012 }
1013
DecodeCCRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1014 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
1015 unsigned RegNo,
1016 uint64_t Address,
1017 const void *Decoder) {
1018 if (RegNo > 31)
1019 return MCDisassembler::Fail;
1020 unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
1021 Inst.addOperand(MCOperand::CreateReg(Reg));
1022 return MCDisassembler::Success;
1023 }
1024
DecodeFCCRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1025 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
1026 unsigned RegNo,
1027 uint64_t Address,
1028 const void *Decoder) {
1029 if (RegNo > 7)
1030 return MCDisassembler::Fail;
1031 unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
1032 Inst.addOperand(MCOperand::CreateReg(Reg));
1033 return MCDisassembler::Success;
1034 }
1035
DecodeFGRCCRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1036 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1037 uint64_t Address,
1038 const void *Decoder) {
1039 if (RegNo > 31)
1040 return MCDisassembler::Fail;
1041
1042 unsigned Reg = getReg(Decoder, Mips::FGRCCRegClassID, RegNo);
1043 Inst.addOperand(MCOperand::CreateReg(Reg));
1044 return MCDisassembler::Success;
1045 }
1046
DecodeMem(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1047 static DecodeStatus DecodeMem(MCInst &Inst,
1048 unsigned Insn,
1049 uint64_t Address,
1050 const void *Decoder) {
1051 int Offset = SignExtend32<16>(Insn & 0xffff);
1052 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1053 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1054
1055 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1056 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1057
1058 if(Inst.getOpcode() == Mips::SC ||
1059 Inst.getOpcode() == Mips::SCD){
1060 Inst.addOperand(MCOperand::CreateReg(Reg));
1061 }
1062
1063 Inst.addOperand(MCOperand::CreateReg(Reg));
1064 Inst.addOperand(MCOperand::CreateReg(Base));
1065 Inst.addOperand(MCOperand::CreateImm(Offset));
1066
1067 return MCDisassembler::Success;
1068 }
1069
DecodeCacheOp(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1070 static DecodeStatus DecodeCacheOp(MCInst &Inst,
1071 unsigned Insn,
1072 uint64_t Address,
1073 const void *Decoder) {
1074 int Offset = SignExtend32<16>(Insn & 0xffff);
1075 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1076 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1077
1078 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1079
1080 Inst.addOperand(MCOperand::CreateReg(Base));
1081 Inst.addOperand(MCOperand::CreateImm(Offset));
1082 Inst.addOperand(MCOperand::CreateImm(Hint));
1083
1084 return MCDisassembler::Success;
1085 }
1086
DecodeCacheOpMM(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1087 static DecodeStatus DecodeCacheOpMM(MCInst &Inst,
1088 unsigned Insn,
1089 uint64_t Address,
1090 const void *Decoder) {
1091 int Offset = SignExtend32<12>(Insn & 0xfff);
1092 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1093 unsigned Hint = fieldFromInstruction(Insn, 21, 5);
1094
1095 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1096
1097 Inst.addOperand(MCOperand::CreateReg(Base));
1098 Inst.addOperand(MCOperand::CreateImm(Offset));
1099 Inst.addOperand(MCOperand::CreateImm(Hint));
1100
1101 return MCDisassembler::Success;
1102 }
1103
DecodeCacheOpR6(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1104 static DecodeStatus DecodeCacheOpR6(MCInst &Inst,
1105 unsigned Insn,
1106 uint64_t Address,
1107 const void *Decoder) {
1108 int Offset = fieldFromInstruction(Insn, 7, 9);
1109 unsigned Hint = fieldFromInstruction(Insn, 16, 5);
1110 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1111
1112 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1113
1114 Inst.addOperand(MCOperand::CreateReg(Base));
1115 Inst.addOperand(MCOperand::CreateImm(Offset));
1116 Inst.addOperand(MCOperand::CreateImm(Hint));
1117
1118 return MCDisassembler::Success;
1119 }
1120
DecodeSyncI(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1121 static DecodeStatus DecodeSyncI(MCInst &Inst,
1122 unsigned Insn,
1123 uint64_t Address,
1124 const void *Decoder) {
1125 int Offset = SignExtend32<16>(Insn & 0xffff);
1126 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1127
1128 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1129
1130 Inst.addOperand(MCOperand::CreateReg(Base));
1131 Inst.addOperand(MCOperand::CreateImm(Offset));
1132
1133 return MCDisassembler::Success;
1134 }
1135
DecodeMSA128Mem(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1136 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1137 uint64_t Address, const void *Decoder) {
1138 int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
1139 unsigned Reg = fieldFromInstruction(Insn, 6, 5);
1140 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1141
1142 Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
1143 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1144
1145 Inst.addOperand(MCOperand::CreateReg(Reg));
1146 Inst.addOperand(MCOperand::CreateReg(Base));
1147
1148 // The immediate field of an LD/ST instruction is scaled which means it must
1149 // be multiplied (when decoding) by the size (in bytes) of the instructions'
1150 // data format.
1151 // .b - 1 byte
1152 // .h - 2 bytes
1153 // .w - 4 bytes
1154 // .d - 8 bytes
1155 switch(Inst.getOpcode())
1156 {
1157 default:
1158 assert (0 && "Unexpected instruction");
1159 return MCDisassembler::Fail;
1160 break;
1161 case Mips::LD_B:
1162 case Mips::ST_B:
1163 Inst.addOperand(MCOperand::CreateImm(Offset));
1164 break;
1165 case Mips::LD_H:
1166 case Mips::ST_H:
1167 Inst.addOperand(MCOperand::CreateImm(Offset * 2));
1168 break;
1169 case Mips::LD_W:
1170 case Mips::ST_W:
1171 Inst.addOperand(MCOperand::CreateImm(Offset * 4));
1172 break;
1173 case Mips::LD_D:
1174 case Mips::ST_D:
1175 Inst.addOperand(MCOperand::CreateImm(Offset * 8));
1176 break;
1177 }
1178
1179 return MCDisassembler::Success;
1180 }
1181
DecodeMemMMImm4(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1182 static DecodeStatus DecodeMemMMImm4(MCInst &Inst,
1183 unsigned Insn,
1184 uint64_t Address,
1185 const void *Decoder) {
1186 unsigned Offset = Insn & 0xf;
1187 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1188 unsigned Base = fieldFromInstruction(Insn, 4, 3);
1189
1190 switch (Inst.getOpcode()) {
1191 case Mips::LBU16_MM:
1192 case Mips::LHU16_MM:
1193 case Mips::LW16_MM:
1194 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1195 == MCDisassembler::Fail)
1196 return MCDisassembler::Fail;
1197 break;
1198 case Mips::SB16_MM:
1199 case Mips::SH16_MM:
1200 case Mips::SW16_MM:
1201 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1202 == MCDisassembler::Fail)
1203 return MCDisassembler::Fail;
1204 break;
1205 }
1206
1207 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1208 == MCDisassembler::Fail)
1209 return MCDisassembler::Fail;
1210
1211 switch (Inst.getOpcode()) {
1212 case Mips::LBU16_MM:
1213 if (Offset == 0xf)
1214 Inst.addOperand(MCOperand::CreateImm(-1));
1215 else
1216 Inst.addOperand(MCOperand::CreateImm(Offset));
1217 break;
1218 case Mips::SB16_MM:
1219 Inst.addOperand(MCOperand::CreateImm(Offset));
1220 break;
1221 case Mips::LHU16_MM:
1222 case Mips::SH16_MM:
1223 Inst.addOperand(MCOperand::CreateImm(Offset << 1));
1224 break;
1225 case Mips::LW16_MM:
1226 case Mips::SW16_MM:
1227 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1228 break;
1229 }
1230
1231 return MCDisassembler::Success;
1232 }
1233
DecodeMemMMSPImm5Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1234 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst,
1235 unsigned Insn,
1236 uint64_t Address,
1237 const void *Decoder) {
1238 unsigned Offset = Insn & 0x1F;
1239 unsigned Reg = fieldFromInstruction(Insn, 5, 5);
1240
1241 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1242
1243 Inst.addOperand(MCOperand::CreateReg(Reg));
1244 Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1245 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1246
1247 return MCDisassembler::Success;
1248 }
1249
DecodeMemMMGPImm7Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1250 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst,
1251 unsigned Insn,
1252 uint64_t Address,
1253 const void *Decoder) {
1254 unsigned Offset = Insn & 0x7F;
1255 unsigned Reg = fieldFromInstruction(Insn, 7, 3);
1256
1257 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1258
1259 Inst.addOperand(MCOperand::CreateReg(Reg));
1260 Inst.addOperand(MCOperand::CreateReg(Mips::GP));
1261 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1262
1263 return MCDisassembler::Success;
1264 }
1265
DecodeMemMMReglistImm4Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1266 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst,
1267 unsigned Insn,
1268 uint64_t Address,
1269 const void *Decoder) {
1270 int Offset = SignExtend32<4>(Insn & 0xf);
1271
1272 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1273 == MCDisassembler::Fail)
1274 return MCDisassembler::Fail;
1275
1276 Inst.addOperand(MCOperand::CreateReg(Mips::SP));
1277 Inst.addOperand(MCOperand::CreateImm(Offset << 2));
1278
1279 return MCDisassembler::Success;
1280 }
1281
DecodeMemMMImm12(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1282 static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
1283 unsigned Insn,
1284 uint64_t Address,
1285 const void *Decoder) {
1286 int Offset = SignExtend32<12>(Insn & 0x0fff);
1287 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1288 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1289
1290 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1291 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1292
1293 switch (Inst.getOpcode()) {
1294 case Mips::SWM32_MM:
1295 case Mips::LWM32_MM:
1296 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1297 == MCDisassembler::Fail)
1298 return MCDisassembler::Fail;
1299 Inst.addOperand(MCOperand::CreateReg(Base));
1300 Inst.addOperand(MCOperand::CreateImm(Offset));
1301 break;
1302 case Mips::SC_MM:
1303 Inst.addOperand(MCOperand::CreateReg(Reg));
1304 // fallthrough
1305 default:
1306 Inst.addOperand(MCOperand::CreateReg(Reg));
1307 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1308 Inst.addOperand(MCOperand::CreateReg(Reg+1));
1309
1310 Inst.addOperand(MCOperand::CreateReg(Base));
1311 Inst.addOperand(MCOperand::CreateImm(Offset));
1312 }
1313
1314 return MCDisassembler::Success;
1315 }
1316
DecodeMemMMImm16(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1317 static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
1318 unsigned Insn,
1319 uint64_t Address,
1320 const void *Decoder) {
1321 int Offset = SignExtend32<16>(Insn & 0xffff);
1322 unsigned Reg = fieldFromInstruction(Insn, 21, 5);
1323 unsigned Base = fieldFromInstruction(Insn, 16, 5);
1324
1325 Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
1326 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1327
1328 Inst.addOperand(MCOperand::CreateReg(Reg));
1329 Inst.addOperand(MCOperand::CreateReg(Base));
1330 Inst.addOperand(MCOperand::CreateImm(Offset));
1331
1332 return MCDisassembler::Success;
1333 }
1334
DecodeFMem(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1335 static DecodeStatus DecodeFMem(MCInst &Inst,
1336 unsigned Insn,
1337 uint64_t Address,
1338 const void *Decoder) {
1339 int Offset = SignExtend32<16>(Insn & 0xffff);
1340 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1341 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1342
1343 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
1344 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1345
1346 Inst.addOperand(MCOperand::CreateReg(Reg));
1347 Inst.addOperand(MCOperand::CreateReg(Base));
1348 Inst.addOperand(MCOperand::CreateImm(Offset));
1349
1350 return MCDisassembler::Success;
1351 }
1352
DecodeFMem2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1353 static DecodeStatus DecodeFMem2(MCInst &Inst,
1354 unsigned Insn,
1355 uint64_t Address,
1356 const void *Decoder) {
1357 int Offset = SignExtend32<16>(Insn & 0xffff);
1358 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1359 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1360
1361 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1362 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1363
1364 Inst.addOperand(MCOperand::CreateReg(Reg));
1365 Inst.addOperand(MCOperand::CreateReg(Base));
1366 Inst.addOperand(MCOperand::CreateImm(Offset));
1367
1368 return MCDisassembler::Success;
1369 }
1370
DecodeFMem3(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1371 static DecodeStatus DecodeFMem3(MCInst &Inst,
1372 unsigned Insn,
1373 uint64_t Address,
1374 const void *Decoder) {
1375 int Offset = SignExtend32<16>(Insn & 0xffff);
1376 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1377 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1378
1379 Reg = getReg(Decoder, Mips::COP3RegClassID, Reg);
1380 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1381
1382 Inst.addOperand(MCOperand::CreateReg(Reg));
1383 Inst.addOperand(MCOperand::CreateReg(Base));
1384 Inst.addOperand(MCOperand::CreateImm(Offset));
1385
1386 return MCDisassembler::Success;
1387 }
1388
DecodeFMemCop2R6(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1389 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst,
1390 unsigned Insn,
1391 uint64_t Address,
1392 const void *Decoder) {
1393 int Offset = SignExtend32<11>(Insn & 0x07ff);
1394 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
1395 unsigned Base = fieldFromInstruction(Insn, 11, 5);
1396
1397 Reg = getReg(Decoder, Mips::COP2RegClassID, Reg);
1398 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1399
1400 Inst.addOperand(MCOperand::CreateReg(Reg));
1401 Inst.addOperand(MCOperand::CreateReg(Base));
1402 Inst.addOperand(MCOperand::CreateImm(Offset));
1403
1404 return MCDisassembler::Success;
1405 }
DecodeSpecial3LlSc(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1406 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
1407 unsigned Insn,
1408 uint64_t Address,
1409 const void *Decoder) {
1410 int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
1411 unsigned Rt = fieldFromInstruction(Insn, 16, 5);
1412 unsigned Base = fieldFromInstruction(Insn, 21, 5);
1413
1414 Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
1415 Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
1416
1417 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1418 Inst.addOperand(MCOperand::CreateReg(Rt));
1419 }
1420
1421 Inst.addOperand(MCOperand::CreateReg(Rt));
1422 Inst.addOperand(MCOperand::CreateReg(Base));
1423 Inst.addOperand(MCOperand::CreateImm(Offset));
1424
1425 return MCDisassembler::Success;
1426 }
1427
DecodeHWRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1428 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
1429 unsigned RegNo,
1430 uint64_t Address,
1431 const void *Decoder) {
1432 // Currently only hardware register 29 is supported.
1433 if (RegNo != 29)
1434 return MCDisassembler::Fail;
1435 Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
1436 return MCDisassembler::Success;
1437 }
1438
DecodeAFGR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1439 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
1440 unsigned RegNo,
1441 uint64_t Address,
1442 const void *Decoder) {
1443 if (RegNo > 30 || RegNo %2)
1444 return MCDisassembler::Fail;
1445
1446 ;
1447 unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
1448 Inst.addOperand(MCOperand::CreateReg(Reg));
1449 return MCDisassembler::Success;
1450 }
1451
DecodeACC64DSPRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1452 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
1453 unsigned RegNo,
1454 uint64_t Address,
1455 const void *Decoder) {
1456 if (RegNo >= 4)
1457 return MCDisassembler::Fail;
1458
1459 unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
1460 Inst.addOperand(MCOperand::CreateReg(Reg));
1461 return MCDisassembler::Success;
1462 }
1463
DecodeHI32DSPRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1464 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
1465 unsigned RegNo,
1466 uint64_t Address,
1467 const void *Decoder) {
1468 if (RegNo >= 4)
1469 return MCDisassembler::Fail;
1470
1471 unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
1472 Inst.addOperand(MCOperand::CreateReg(Reg));
1473 return MCDisassembler::Success;
1474 }
1475
DecodeLO32DSPRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1476 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
1477 unsigned RegNo,
1478 uint64_t Address,
1479 const void *Decoder) {
1480 if (RegNo >= 4)
1481 return MCDisassembler::Fail;
1482
1483 unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
1484 Inst.addOperand(MCOperand::CreateReg(Reg));
1485 return MCDisassembler::Success;
1486 }
1487
DecodeMSA128BRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1488 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
1489 unsigned RegNo,
1490 uint64_t Address,
1491 const void *Decoder) {
1492 if (RegNo > 31)
1493 return MCDisassembler::Fail;
1494
1495 unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
1496 Inst.addOperand(MCOperand::CreateReg(Reg));
1497 return MCDisassembler::Success;
1498 }
1499
DecodeMSA128HRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1500 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
1501 unsigned RegNo,
1502 uint64_t Address,
1503 const void *Decoder) {
1504 if (RegNo > 31)
1505 return MCDisassembler::Fail;
1506
1507 unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
1508 Inst.addOperand(MCOperand::CreateReg(Reg));
1509 return MCDisassembler::Success;
1510 }
1511
DecodeMSA128WRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1512 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
1513 unsigned RegNo,
1514 uint64_t Address,
1515 const void *Decoder) {
1516 if (RegNo > 31)
1517 return MCDisassembler::Fail;
1518
1519 unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
1520 Inst.addOperand(MCOperand::CreateReg(Reg));
1521 return MCDisassembler::Success;
1522 }
1523
DecodeMSA128DRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1524 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
1525 unsigned RegNo,
1526 uint64_t Address,
1527 const void *Decoder) {
1528 if (RegNo > 31)
1529 return MCDisassembler::Fail;
1530
1531 unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
1532 Inst.addOperand(MCOperand::CreateReg(Reg));
1533 return MCDisassembler::Success;
1534 }
1535
DecodeMSACtrlRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1536 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
1537 unsigned RegNo,
1538 uint64_t Address,
1539 const void *Decoder) {
1540 if (RegNo > 7)
1541 return MCDisassembler::Fail;
1542
1543 unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
1544 Inst.addOperand(MCOperand::CreateReg(Reg));
1545 return MCDisassembler::Success;
1546 }
1547
DecodeCOP2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)1548 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst,
1549 unsigned RegNo,
1550 uint64_t Address,
1551 const void *Decoder) {
1552 if (RegNo > 31)
1553 return MCDisassembler::Fail;
1554
1555 unsigned Reg = getReg(Decoder, Mips::COP2RegClassID, RegNo);
1556 Inst.addOperand(MCOperand::CreateReg(Reg));
1557 return MCDisassembler::Success;
1558 }
1559
DecodeBranchTarget(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)1560 static DecodeStatus DecodeBranchTarget(MCInst &Inst,
1561 unsigned Offset,
1562 uint64_t Address,
1563 const void *Decoder) {
1564 int32_t BranchOffset = (SignExtend32<16>(Offset) * 4) + 4;
1565 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1566 return MCDisassembler::Success;
1567 }
1568
DecodeJumpTarget(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1569 static DecodeStatus DecodeJumpTarget(MCInst &Inst,
1570 unsigned Insn,
1571 uint64_t Address,
1572 const void *Decoder) {
1573
1574 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
1575 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1576 return MCDisassembler::Success;
1577 }
1578
DecodeBranchTarget21(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)1579 static DecodeStatus DecodeBranchTarget21(MCInst &Inst,
1580 unsigned Offset,
1581 uint64_t Address,
1582 const void *Decoder) {
1583 int32_t BranchOffset = SignExtend32<21>(Offset) * 4;
1584
1585 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1586 return MCDisassembler::Success;
1587 }
1588
DecodeBranchTarget26(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)1589 static DecodeStatus DecodeBranchTarget26(MCInst &Inst,
1590 unsigned Offset,
1591 uint64_t Address,
1592 const void *Decoder) {
1593 int32_t BranchOffset = SignExtend32<26>(Offset) * 4;
1594
1595 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1596 return MCDisassembler::Success;
1597 }
1598
DecodeBranchTarget7MM(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)1599 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst,
1600 unsigned Offset,
1601 uint64_t Address,
1602 const void *Decoder) {
1603 int32_t BranchOffset = SignExtend32<7>(Offset) << 1;
1604 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1605 return MCDisassembler::Success;
1606 }
1607
DecodeBranchTarget10MM(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)1608 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst,
1609 unsigned Offset,
1610 uint64_t Address,
1611 const void *Decoder) {
1612 int32_t BranchOffset = SignExtend32<10>(Offset) << 1;
1613 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1614 return MCDisassembler::Success;
1615 }
1616
DecodeBranchTargetMM(MCInst & Inst,unsigned Offset,uint64_t Address,const void * Decoder)1617 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst,
1618 unsigned Offset,
1619 uint64_t Address,
1620 const void *Decoder) {
1621 int32_t BranchOffset = SignExtend32<16>(Offset) * 2;
1622 Inst.addOperand(MCOperand::CreateImm(BranchOffset));
1623 return MCDisassembler::Success;
1624 }
1625
DecodeJumpTargetMM(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1626 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
1627 unsigned Insn,
1628 uint64_t Address,
1629 const void *Decoder) {
1630 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
1631 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
1632 return MCDisassembler::Success;
1633 }
1634
DecodeAddiur2Simm7(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)1635 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst,
1636 unsigned Value,
1637 uint64_t Address,
1638 const void *Decoder) {
1639 if (Value == 0)
1640 Inst.addOperand(MCOperand::CreateImm(1));
1641 else if (Value == 0x7)
1642 Inst.addOperand(MCOperand::CreateImm(-1));
1643 else
1644 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1645 return MCDisassembler::Success;
1646 }
1647
DecodeUImm6Lsl2(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)1648 static DecodeStatus DecodeUImm6Lsl2(MCInst &Inst,
1649 unsigned Value,
1650 uint64_t Address,
1651 const void *Decoder) {
1652 Inst.addOperand(MCOperand::CreateImm(Value << 2));
1653 return MCDisassembler::Success;
1654 }
1655
DecodeLiSimm7(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)1656 static DecodeStatus DecodeLiSimm7(MCInst &Inst,
1657 unsigned Value,
1658 uint64_t Address,
1659 const void *Decoder) {
1660 if (Value == 0x7F)
1661 Inst.addOperand(MCOperand::CreateImm(-1));
1662 else
1663 Inst.addOperand(MCOperand::CreateImm(Value));
1664 return MCDisassembler::Success;
1665 }
1666
DecodeSimm4(MCInst & Inst,unsigned Value,uint64_t Address,const void * Decoder)1667 static DecodeStatus DecodeSimm4(MCInst &Inst,
1668 unsigned Value,
1669 uint64_t Address,
1670 const void *Decoder) {
1671 Inst.addOperand(MCOperand::CreateImm(SignExtend32<4>(Value)));
1672 return MCDisassembler::Success;
1673 }
1674
DecodeSimm16(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1675 static DecodeStatus DecodeSimm16(MCInst &Inst,
1676 unsigned Insn,
1677 uint64_t Address,
1678 const void *Decoder) {
1679 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
1680 return MCDisassembler::Success;
1681 }
1682
DecodeLSAImm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1683 static DecodeStatus DecodeLSAImm(MCInst &Inst,
1684 unsigned Insn,
1685 uint64_t Address,
1686 const void *Decoder) {
1687 // We add one to the immediate field as it was encoded as 'imm - 1'.
1688 Inst.addOperand(MCOperand::CreateImm(Insn + 1));
1689 return MCDisassembler::Success;
1690 }
1691
DecodeInsSize(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1692 static DecodeStatus DecodeInsSize(MCInst &Inst,
1693 unsigned Insn,
1694 uint64_t Address,
1695 const void *Decoder) {
1696 // First we need to grab the pos(lsb) from MCInst.
1697 int Pos = Inst.getOperand(2).getImm();
1698 int Size = (int) Insn - Pos + 1;
1699 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1700 return MCDisassembler::Success;
1701 }
1702
DecodeExtSize(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1703 static DecodeStatus DecodeExtSize(MCInst &Inst,
1704 unsigned Insn,
1705 uint64_t Address,
1706 const void *Decoder) {
1707 int Size = (int) Insn + 1;
1708 Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
1709 return MCDisassembler::Success;
1710 }
1711
DecodeSimm19Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1712 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
1713 uint64_t Address, const void *Decoder) {
1714 Inst.addOperand(MCOperand::CreateImm(SignExtend32<19>(Insn) * 4));
1715 return MCDisassembler::Success;
1716 }
1717
DecodeSimm18Lsl3(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1718 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
1719 uint64_t Address, const void *Decoder) {
1720 Inst.addOperand(MCOperand::CreateImm(SignExtend32<18>(Insn) * 8));
1721 return MCDisassembler::Success;
1722 }
1723
DecodeSimm9SP(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1724 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn,
1725 uint64_t Address, const void *Decoder) {
1726 int32_t DecodedValue;
1727 switch (Insn) {
1728 case 0: DecodedValue = 256; break;
1729 case 1: DecodedValue = 257; break;
1730 case 510: DecodedValue = -258; break;
1731 case 511: DecodedValue = -257; break;
1732 default: DecodedValue = SignExtend32<9>(Insn); break;
1733 }
1734 Inst.addOperand(MCOperand::CreateImm(DecodedValue * 4));
1735 return MCDisassembler::Success;
1736 }
1737
DecodeANDI16Imm(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1738 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
1739 uint64_t Address, const void *Decoder) {
1740 // Insn must be >= 0, since it is unsigned that condition is always true.
1741 assert(Insn < 16);
1742 int32_t DecodedValues[] = {128, 1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64,
1743 255, 32768, 65535};
1744 Inst.addOperand(MCOperand::CreateImm(DecodedValues[Insn]));
1745 return MCDisassembler::Success;
1746 }
1747
DecodeUImm5lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1748 static DecodeStatus DecodeUImm5lsl2(MCInst &Inst, unsigned Insn,
1749 uint64_t Address, const void *Decoder) {
1750 Inst.addOperand(MCOperand::CreateImm(Insn << 2));
1751 return MCDisassembler::Success;
1752 }
1753
DecodeRegListOperand(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1754 static DecodeStatus DecodeRegListOperand(MCInst &Inst,
1755 unsigned Insn,
1756 uint64_t Address,
1757 const void *Decoder) {
1758 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5,
1759 Mips::S6, Mips::FP};
1760 unsigned RegNum;
1761
1762 unsigned RegLst = fieldFromInstruction(Insn, 21, 5);
1763 // Empty register lists are not allowed.
1764 if (RegLst == 0)
1765 return MCDisassembler::Fail;
1766
1767 RegNum = RegLst & 0xf;
1768 for (unsigned i = 0; i < RegNum; i++)
1769 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1770
1771 if (RegLst & 0x10)
1772 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1773
1774 return MCDisassembler::Success;
1775 }
1776
DecodeRegListOperand16(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1777 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
1778 uint64_t Address,
1779 const void *Decoder) {
1780 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3};
1781 unsigned RegLst = fieldFromInstruction(Insn, 4, 2);
1782 unsigned RegNum = RegLst & 0x3;
1783
1784 for (unsigned i = 0; i <= RegNum; i++)
1785 Inst.addOperand(MCOperand::CreateReg(Regs[i]));
1786
1787 Inst.addOperand(MCOperand::CreateReg(Mips::RA));
1788
1789 return MCDisassembler::Success;
1790 }
1791
DecodeMovePRegPair(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1792 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn,
1793 uint64_t Address, const void *Decoder) {
1794
1795 unsigned RegPair = fieldFromInstruction(Insn, 7, 3);
1796
1797 switch (RegPair) {
1798 default:
1799 return MCDisassembler::Fail;
1800 case 0:
1801 Inst.addOperand(MCOperand::CreateReg(Mips::A1));
1802 Inst.addOperand(MCOperand::CreateReg(Mips::A2));
1803 break;
1804 case 1:
1805 Inst.addOperand(MCOperand::CreateReg(Mips::A1));
1806 Inst.addOperand(MCOperand::CreateReg(Mips::A3));
1807 break;
1808 case 2:
1809 Inst.addOperand(MCOperand::CreateReg(Mips::A2));
1810 Inst.addOperand(MCOperand::CreateReg(Mips::A3));
1811 break;
1812 case 3:
1813 Inst.addOperand(MCOperand::CreateReg(Mips::A0));
1814 Inst.addOperand(MCOperand::CreateReg(Mips::S5));
1815 break;
1816 case 4:
1817 Inst.addOperand(MCOperand::CreateReg(Mips::A0));
1818 Inst.addOperand(MCOperand::CreateReg(Mips::S6));
1819 break;
1820 case 5:
1821 Inst.addOperand(MCOperand::CreateReg(Mips::A0));
1822 Inst.addOperand(MCOperand::CreateReg(Mips::A1));
1823 break;
1824 case 6:
1825 Inst.addOperand(MCOperand::CreateReg(Mips::A0));
1826 Inst.addOperand(MCOperand::CreateReg(Mips::A2));
1827 break;
1828 case 7:
1829 Inst.addOperand(MCOperand::CreateReg(Mips::A0));
1830 Inst.addOperand(MCOperand::CreateReg(Mips::A3));
1831 break;
1832 }
1833
1834 return MCDisassembler::Success;
1835 }
1836
DecodeSimm23Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const void * Decoder)1837 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
1838 uint64_t Address, const void *Decoder) {
1839 Inst.addOperand(MCOperand::CreateImm(SignExtend32<23>(Insn) << 2));
1840 return MCDisassembler::Success;
1841 }
1842