1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the interfaces that Sparc uses to lower LLVM code into a
11 // selection DAG.
12 //
13 //===----------------------------------------------------------------------===//
14
15 #include "SparcISelLowering.h"
16 #include "MCTargetDesc/SparcMCExpr.h"
17 #include "SparcMachineFunctionInfo.h"
18 #include "SparcRegisterInfo.h"
19 #include "SparcTargetMachine.h"
20 #include "SparcTargetObjectFile.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/DerivedTypes.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/ErrorHandling.h"
32 using namespace llvm;
33
34
35 //===----------------------------------------------------------------------===//
36 // Calling Convention Implementation
37 //===----------------------------------------------------------------------===//
38
CC_Sparc_Assign_SRet(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)39 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
40 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags, CCState &State)
42 {
43 assert (ArgFlags.isSRet());
44
45 // Assign SRet argument.
46 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
47 0,
48 LocVT, LocInfo));
49 return true;
50 }
51
CC_Sparc_Assign_f64(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)52 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
53 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
54 ISD::ArgFlagsTy &ArgFlags, CCState &State)
55 {
56 static const MCPhysReg RegList[] = {
57 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
58 };
59 // Try to get first reg.
60 if (unsigned Reg = State.AllocateReg(RegList)) {
61 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
62 } else {
63 // Assign whole thing in stack.
64 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
65 State.AllocateStack(8,4),
66 LocVT, LocInfo));
67 return true;
68 }
69
70 // Try to get second reg.
71 if (unsigned Reg = State.AllocateReg(RegList))
72 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
73 else
74 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
75 State.AllocateStack(4,4),
76 LocVT, LocInfo));
77 return true;
78 }
79
80 // Allocate a full-sized argument for the 64-bit ABI.
CC_Sparc64_Full(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)81 static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT,
82 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
83 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
84 assert((LocVT == MVT::f32 || LocVT == MVT::f128
85 || LocVT.getSizeInBits() == 64) &&
86 "Can't handle non-64 bits locations");
87
88 // Stack space is allocated for all arguments starting from [%fp+BIAS+128].
89 unsigned size = (LocVT == MVT::f128) ? 16 : 8;
90 unsigned alignment = (LocVT == MVT::f128) ? 16 : 8;
91 unsigned Offset = State.AllocateStack(size, alignment);
92 unsigned Reg = 0;
93
94 if (LocVT == MVT::i64 && Offset < 6*8)
95 // Promote integers to %i0-%i5.
96 Reg = SP::I0 + Offset/8;
97 else if (LocVT == MVT::f64 && Offset < 16*8)
98 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15).
99 Reg = SP::D0 + Offset/8;
100 else if (LocVT == MVT::f32 && Offset < 16*8)
101 // Promote floats to %f1, %f3, ...
102 Reg = SP::F1 + Offset/4;
103 else if (LocVT == MVT::f128 && Offset < 16*8)
104 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7).
105 Reg = SP::Q0 + Offset/16;
106
107 // Promote to register when possible, otherwise use the stack slot.
108 if (Reg) {
109 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
110 return true;
111 }
112
113 // This argument goes on the stack in an 8-byte slot.
114 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to
115 // the right-aligned float. The first 4 bytes of the stack slot are undefined.
116 if (LocVT == MVT::f32)
117 Offset += 4;
118
119 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
120 return true;
121 }
122
123 // Allocate a half-sized argument for the 64-bit ABI.
124 //
125 // This is used when passing { float, int } structs by value in registers.
CC_Sparc64_Half(unsigned & ValNo,MVT & ValVT,MVT & LocVT,CCValAssign::LocInfo & LocInfo,ISD::ArgFlagsTy & ArgFlags,CCState & State)126 static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT,
127 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
128 ISD::ArgFlagsTy &ArgFlags, CCState &State) {
129 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations");
130 unsigned Offset = State.AllocateStack(4, 4);
131
132 if (LocVT == MVT::f32 && Offset < 16*8) {
133 // Promote floats to %f0-%f31.
134 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
135 LocVT, LocInfo));
136 return true;
137 }
138
139 if (LocVT == MVT::i32 && Offset < 6*8) {
140 // Promote integers to %i0-%i5, using half the register.
141 unsigned Reg = SP::I0 + Offset/8;
142 LocVT = MVT::i64;
143 LocInfo = CCValAssign::AExt;
144
145 // Set the Custom bit if this i32 goes in the high bits of a register.
146 if (Offset % 8 == 0)
147 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg,
148 LocVT, LocInfo));
149 else
150 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
151 return true;
152 }
153
154 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
155 return true;
156 }
157
158 #include "SparcGenCallingConv.inc"
159
160 // The calling conventions in SparcCallingConv.td are described in terms of the
161 // callee's register window. This function translates registers to the
162 // corresponding caller window %o register.
toCallerWindow(unsigned Reg)163 static unsigned toCallerWindow(unsigned Reg) {
164 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum");
165 if (Reg >= SP::I0 && Reg <= SP::I7)
166 return Reg - SP::I0 + SP::O0;
167 return Reg;
168 }
169
170 SDValue
LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,SDLoc DL,SelectionDAG & DAG) const171 SparcTargetLowering::LowerReturn(SDValue Chain,
172 CallingConv::ID CallConv, bool IsVarArg,
173 const SmallVectorImpl<ISD::OutputArg> &Outs,
174 const SmallVectorImpl<SDValue> &OutVals,
175 SDLoc DL, SelectionDAG &DAG) const {
176 if (Subtarget->is64Bit())
177 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
178 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG);
179 }
180
181 SDValue
LowerReturn_32(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,SDLoc DL,SelectionDAG & DAG) const182 SparcTargetLowering::LowerReturn_32(SDValue Chain,
183 CallingConv::ID CallConv, bool IsVarArg,
184 const SmallVectorImpl<ISD::OutputArg> &Outs,
185 const SmallVectorImpl<SDValue> &OutVals,
186 SDLoc DL, SelectionDAG &DAG) const {
187 MachineFunction &MF = DAG.getMachineFunction();
188
189 // CCValAssign - represent the assignment of the return value to locations.
190 SmallVector<CCValAssign, 16> RVLocs;
191
192 // CCState - Info about the registers and stack slot.
193 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
194 *DAG.getContext());
195
196 // Analyze return values.
197 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
198
199 SDValue Flag;
200 SmallVector<SDValue, 4> RetOps(1, Chain);
201 // Make room for the return address offset.
202 RetOps.push_back(SDValue());
203
204 // Copy the result values into the output registers.
205 for (unsigned i = 0; i != RVLocs.size(); ++i) {
206 CCValAssign &VA = RVLocs[i];
207 assert(VA.isRegLoc() && "Can only return in registers!");
208
209 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(),
210 OutVals[i], Flag);
211
212 // Guarantee that all emitted copies are stuck together with flags.
213 Flag = Chain.getValue(1);
214 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
215 }
216
217 unsigned RetAddrOffset = 8; // Call Inst + Delay Slot
218 // If the function returns a struct, copy the SRetReturnReg to I0
219 if (MF.getFunction()->hasStructRetAttr()) {
220 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
221 unsigned Reg = SFI->getSRetReturnReg();
222 if (!Reg)
223 llvm_unreachable("sret virtual register not created in the entry block");
224 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
225 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag);
226 Flag = Chain.getValue(1);
227 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy()));
228 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp
229 }
230
231 RetOps[0] = Chain; // Update chain.
232 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32);
233
234 // Add the flag if we have it.
235 if (Flag.getNode())
236 RetOps.push_back(Flag);
237
238 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
239 }
240
241 // Lower return values for the 64-bit ABI.
242 // Return values are passed the exactly the same way as function arguments.
243 SDValue
LowerReturn_64(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,SDLoc DL,SelectionDAG & DAG) const244 SparcTargetLowering::LowerReturn_64(SDValue Chain,
245 CallingConv::ID CallConv, bool IsVarArg,
246 const SmallVectorImpl<ISD::OutputArg> &Outs,
247 const SmallVectorImpl<SDValue> &OutVals,
248 SDLoc DL, SelectionDAG &DAG) const {
249 // CCValAssign - represent the assignment of the return value to locations.
250 SmallVector<CCValAssign, 16> RVLocs;
251
252 // CCState - Info about the registers and stack slot.
253 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
254 *DAG.getContext());
255
256 // Analyze return values.
257 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64);
258
259 SDValue Flag;
260 SmallVector<SDValue, 4> RetOps(1, Chain);
261
262 // The second operand on the return instruction is the return address offset.
263 // The return address is always %i7+8 with the 64-bit ABI.
264 RetOps.push_back(DAG.getConstant(8, MVT::i32));
265
266 // Copy the result values into the output registers.
267 for (unsigned i = 0; i != RVLocs.size(); ++i) {
268 CCValAssign &VA = RVLocs[i];
269 assert(VA.isRegLoc() && "Can only return in registers!");
270 SDValue OutVal = OutVals[i];
271
272 // Integer return values must be sign or zero extended by the callee.
273 switch (VA.getLocInfo()) {
274 case CCValAssign::Full: break;
275 case CCValAssign::SExt:
276 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal);
277 break;
278 case CCValAssign::ZExt:
279 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal);
280 break;
281 case CCValAssign::AExt:
282 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal);
283 break;
284 default:
285 llvm_unreachable("Unknown loc info!");
286 }
287
288 // The custom bit on an i32 return value indicates that it should be passed
289 // in the high bits of the register.
290 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
291 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal,
292 DAG.getConstant(32, MVT::i32));
293
294 // The next value may go in the low bits of the same register.
295 // Handle both at once.
296 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) {
297 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]);
298 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV);
299 // Skip the next value, it's already done.
300 ++i;
301 }
302 }
303
304 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag);
305
306 // Guarantee that all emitted copies are stuck together with flags.
307 Flag = Chain.getValue(1);
308 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
309 }
310
311 RetOps[0] = Chain; // Update chain.
312
313 // Add the flag if we have it.
314 if (Flag.getNode())
315 RetOps.push_back(Flag);
316
317 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, RetOps);
318 }
319
320 SDValue SparcTargetLowering::
LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const321 LowerFormalArguments(SDValue Chain,
322 CallingConv::ID CallConv,
323 bool IsVarArg,
324 const SmallVectorImpl<ISD::InputArg> &Ins,
325 SDLoc DL,
326 SelectionDAG &DAG,
327 SmallVectorImpl<SDValue> &InVals) const {
328 if (Subtarget->is64Bit())
329 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
330 DL, DAG, InVals);
331 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
332 DL, DAG, InVals);
333 }
334
335 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
336 /// passed in either one or two GPRs, including FP values. TODO: we should
337 /// pass FP values in FP registers for fastcc functions.
338 SDValue SparcTargetLowering::
LowerFormalArguments_32(SDValue Chain,CallingConv::ID CallConv,bool isVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc dl,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const339 LowerFormalArguments_32(SDValue Chain,
340 CallingConv::ID CallConv,
341 bool isVarArg,
342 const SmallVectorImpl<ISD::InputArg> &Ins,
343 SDLoc dl,
344 SelectionDAG &DAG,
345 SmallVectorImpl<SDValue> &InVals) const {
346 MachineFunction &MF = DAG.getMachineFunction();
347 MachineRegisterInfo &RegInfo = MF.getRegInfo();
348 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
349
350 // Assign locations to all of the incoming arguments.
351 SmallVector<CCValAssign, 16> ArgLocs;
352 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
353 *DAG.getContext());
354 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
355
356 const unsigned StackOffset = 92;
357
358 unsigned InIdx = 0;
359 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
360 CCValAssign &VA = ArgLocs[i];
361
362 if (Ins[InIdx].Flags.isSRet()) {
363 if (InIdx != 0)
364 report_fatal_error("sparc only supports sret on the first parameter");
365 // Get SRet from [%fp+64].
366 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true);
367 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
368 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
369 MachinePointerInfo(),
370 false, false, false, 0);
371 InVals.push_back(Arg);
372 continue;
373 }
374
375 if (VA.isRegLoc()) {
376 if (VA.needsCustom()) {
377 assert(VA.getLocVT() == MVT::f64);
378 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
379 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi);
380 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
381
382 assert(i+1 < e);
383 CCValAssign &NextVA = ArgLocs[++i];
384
385 SDValue LoVal;
386 if (NextVA.isMemLoc()) {
387 int FrameIdx = MF.getFrameInfo()->
388 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true);
389 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
390 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
391 MachinePointerInfo(),
392 false, false, false, 0);
393 } else {
394 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
395 &SP::IntRegsRegClass);
396 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
397 }
398 SDValue WholeValue =
399 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
400 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
401 InVals.push_back(WholeValue);
402 continue;
403 }
404 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
405 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
406 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
407 if (VA.getLocVT() == MVT::f32)
408 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg);
409 else if (VA.getLocVT() != MVT::i32) {
410 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg,
411 DAG.getValueType(VA.getLocVT()));
412 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg);
413 }
414 InVals.push_back(Arg);
415 continue;
416 }
417
418 assert(VA.isMemLoc());
419
420 unsigned Offset = VA.getLocMemOffset()+StackOffset;
421
422 if (VA.needsCustom()) {
423 assert(VA.getValVT() == MVT::f64);
424 // If it is double-word aligned, just load.
425 if (Offset % 8 == 0) {
426 int FI = MF.getFrameInfo()->CreateFixedObject(8,
427 Offset,
428 true);
429 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
430 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
431 MachinePointerInfo(),
432 false,false, false, 0);
433 InVals.push_back(Load);
434 continue;
435 }
436
437 int FI = MF.getFrameInfo()->CreateFixedObject(4,
438 Offset,
439 true);
440 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
441 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
442 MachinePointerInfo(),
443 false, false, false, 0);
444 int FI2 = MF.getFrameInfo()->CreateFixedObject(4,
445 Offset+4,
446 true);
447 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy());
448
449 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2,
450 MachinePointerInfo(),
451 false, false, false, 0);
452
453 SDValue WholeValue =
454 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
455 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue);
456 InVals.push_back(WholeValue);
457 continue;
458 }
459
460 int FI = MF.getFrameInfo()->CreateFixedObject(4,
461 Offset,
462 true);
463 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
464 SDValue Load ;
465 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) {
466 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr,
467 MachinePointerInfo(),
468 false, false, false, 0);
469 } else {
470 ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
471 // Sparc is big endian, so add an offset based on the ObjectVT.
472 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8);
473 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
474 DAG.getConstant(Offset, MVT::i32));
475 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
476 MachinePointerInfo(),
477 VA.getValVT(), false, false, false,0);
478 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load);
479 }
480 InVals.push_back(Load);
481 }
482
483 if (MF.getFunction()->hasStructRetAttr()) {
484 // Copy the SRet Argument to SRetReturnReg.
485 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>();
486 unsigned Reg = SFI->getSRetReturnReg();
487 if (!Reg) {
488 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass);
489 SFI->setSRetReturnReg(Reg);
490 }
491 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
492 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
493 }
494
495 // Store remaining ArgRegs to the stack if this is a varargs function.
496 if (isVarArg) {
497 static const MCPhysReg ArgRegs[] = {
498 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
499 };
500 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs);
501 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
502 unsigned ArgOffset = CCInfo.getNextStackOffset();
503 if (NumAllocated == 6)
504 ArgOffset += StackOffset;
505 else {
506 assert(!ArgOffset);
507 ArgOffset = 68+4*NumAllocated;
508 }
509
510 // Remember the vararg offset for the va_start implementation.
511 FuncInfo->setVarArgsFrameOffset(ArgOffset);
512
513 std::vector<SDValue> OutChains;
514
515 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
516 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
517 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
518 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
519
520 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset,
521 true);
522 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
523
524 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr,
525 MachinePointerInfo(),
526 false, false, 0));
527 ArgOffset += 4;
528 }
529
530 if (!OutChains.empty()) {
531 OutChains.push_back(Chain);
532 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
533 }
534 }
535
536 return Chain;
537 }
538
539 // Lower formal arguments for the 64 bit ABI.
540 SDValue SparcTargetLowering::
LowerFormalArguments_64(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,SDLoc DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const541 LowerFormalArguments_64(SDValue Chain,
542 CallingConv::ID CallConv,
543 bool IsVarArg,
544 const SmallVectorImpl<ISD::InputArg> &Ins,
545 SDLoc DL,
546 SelectionDAG &DAG,
547 SmallVectorImpl<SDValue> &InVals) const {
548 MachineFunction &MF = DAG.getMachineFunction();
549
550 // Analyze arguments according to CC_Sparc64.
551 SmallVector<CCValAssign, 16> ArgLocs;
552 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
553 *DAG.getContext());
554 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
555
556 // The argument array begins at %fp+BIAS+128, after the register save area.
557 const unsigned ArgArea = 128;
558
559 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
560 CCValAssign &VA = ArgLocs[i];
561 if (VA.isRegLoc()) {
562 // This argument is passed in a register.
563 // All integer register arguments are promoted by the caller to i64.
564
565 // Create a virtual register for the promoted live-in value.
566 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
567 getRegClassFor(VA.getLocVT()));
568 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
569
570 // Get the high bits for i32 struct elements.
571 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
572 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg,
573 DAG.getConstant(32, MVT::i32));
574
575 // The caller promoted the argument, so insert an Assert?ext SDNode so we
576 // won't promote the value again in this function.
577 switch (VA.getLocInfo()) {
578 case CCValAssign::SExt:
579 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
580 DAG.getValueType(VA.getValVT()));
581 break;
582 case CCValAssign::ZExt:
583 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
584 DAG.getValueType(VA.getValVT()));
585 break;
586 default:
587 break;
588 }
589
590 // Truncate the register down to the argument type.
591 if (VA.isExtInLoc())
592 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
593
594 InVals.push_back(Arg);
595 continue;
596 }
597
598 // The registers are exhausted. This argument was passed on the stack.
599 assert(VA.isMemLoc());
600 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the
601 // beginning of the arguments area at %fp+BIAS+128.
602 unsigned Offset = VA.getLocMemOffset() + ArgArea;
603 unsigned ValSize = VA.getValVT().getSizeInBits() / 8;
604 // Adjust offset for extended arguments, SPARC is big-endian.
605 // The caller will have written the full slot with extended bytes, but we
606 // prefer our own extending loads.
607 if (VA.isExtInLoc())
608 Offset += 8 - ValSize;
609 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true);
610 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain,
611 DAG.getFrameIndex(FI, getPointerTy()),
612 MachinePointerInfo::getFixedStack(FI),
613 false, false, false, 0));
614 }
615
616 if (!IsVarArg)
617 return Chain;
618
619 // This function takes variable arguments, some of which may have been passed
620 // in registers %i0-%i5. Variable floating point arguments are never passed
621 // in floating point registers. They go on %i0-%i5 or on the stack like
622 // integer arguments.
623 //
624 // The va_start intrinsic needs to know the offset to the first variable
625 // argument.
626 unsigned ArgOffset = CCInfo.getNextStackOffset();
627 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
628 // Skip the 128 bytes of register save area.
629 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea +
630 Subtarget->getStackPointerBias());
631
632 // Save the variable arguments that were passed in registers.
633 // The caller is required to reserve stack space for 6 arguments regardless
634 // of how many arguments were actually passed.
635 SmallVector<SDValue, 8> OutChains;
636 for (; ArgOffset < 6*8; ArgOffset += 8) {
637 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass);
638 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
639 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true);
640 OutChains.push_back(DAG.getStore(Chain, DL, VArg,
641 DAG.getFrameIndex(FI, getPointerTy()),
642 MachinePointerInfo::getFixedStack(FI),
643 false, false, 0));
644 }
645
646 if (!OutChains.empty())
647 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains);
648
649 return Chain;
650 }
651
652 SDValue
LowerCall(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const653 SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
654 SmallVectorImpl<SDValue> &InVals) const {
655 if (Subtarget->is64Bit())
656 return LowerCall_64(CLI, InVals);
657 return LowerCall_32(CLI, InVals);
658 }
659
hasReturnsTwiceAttr(SelectionDAG & DAG,SDValue Callee,ImmutableCallSite * CS)660 static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee,
661 ImmutableCallSite *CS) {
662 if (CS)
663 return CS->hasFnAttr(Attribute::ReturnsTwice);
664
665 const Function *CalleeFn = nullptr;
666 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
667 CalleeFn = dyn_cast<Function>(G->getGlobal());
668 } else if (ExternalSymbolSDNode *E =
669 dyn_cast<ExternalSymbolSDNode>(Callee)) {
670 const Function *Fn = DAG.getMachineFunction().getFunction();
671 const Module *M = Fn->getParent();
672 const char *CalleeName = E->getSymbol();
673 CalleeFn = M->getFunction(CalleeName);
674 }
675
676 if (!CalleeFn)
677 return false;
678 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice);
679 }
680
681 // Lower a call for the 32-bit ABI.
682 SDValue
LowerCall_32(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const683 SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI,
684 SmallVectorImpl<SDValue> &InVals) const {
685 SelectionDAG &DAG = CLI.DAG;
686 SDLoc &dl = CLI.DL;
687 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
688 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
689 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
690 SDValue Chain = CLI.Chain;
691 SDValue Callee = CLI.Callee;
692 bool &isTailCall = CLI.IsTailCall;
693 CallingConv::ID CallConv = CLI.CallConv;
694 bool isVarArg = CLI.IsVarArg;
695
696 // Sparc target does not yet support tail call optimization.
697 isTailCall = false;
698
699 // Analyze operands of the call, assigning locations to each operand.
700 SmallVector<CCValAssign, 16> ArgLocs;
701 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
702 *DAG.getContext());
703 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
704
705 // Get the size of the outgoing arguments stack space requirement.
706 unsigned ArgsSize = CCInfo.getNextStackOffset();
707
708 // Keep stack frames 8-byte aligned.
709 ArgsSize = (ArgsSize+7) & ~7;
710
711 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
712
713 // Create local copies for byval args.
714 SmallVector<SDValue, 8> ByValArgs;
715 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
716 ISD::ArgFlagsTy Flags = Outs[i].Flags;
717 if (!Flags.isByVal())
718 continue;
719
720 SDValue Arg = OutVals[i];
721 unsigned Size = Flags.getByValSize();
722 unsigned Align = Flags.getByValAlign();
723
724 int FI = MFI->CreateStackObject(Size, Align, false);
725 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
726 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
727
728 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align,
729 false, // isVolatile,
730 (Size <= 32), // AlwaysInline if size <= 32,
731 false, // isTailCall
732 MachinePointerInfo(), MachinePointerInfo());
733 ByValArgs.push_back(FIPtr);
734 }
735
736 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
737 dl);
738
739 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
740 SmallVector<SDValue, 8> MemOpChains;
741
742 const unsigned StackOffset = 92;
743 bool hasStructRetAttr = false;
744 // Walk the register/memloc assignments, inserting copies/loads.
745 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size();
746 i != e;
747 ++i, ++realArgIdx) {
748 CCValAssign &VA = ArgLocs[i];
749 SDValue Arg = OutVals[realArgIdx];
750
751 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
752
753 // Use local copy if it is a byval arg.
754 if (Flags.isByVal())
755 Arg = ByValArgs[byvalArgIdx++];
756
757 // Promote the value if needed.
758 switch (VA.getLocInfo()) {
759 default: llvm_unreachable("Unknown loc info!");
760 case CCValAssign::Full: break;
761 case CCValAssign::SExt:
762 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
763 break;
764 case CCValAssign::ZExt:
765 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
766 break;
767 case CCValAssign::AExt:
768 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
769 break;
770 case CCValAssign::BCvt:
771 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
772 break;
773 }
774
775 if (Flags.isSRet()) {
776 assert(VA.needsCustom());
777 // store SRet argument in %sp+64
778 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
779 SDValue PtrOff = DAG.getIntPtrConstant(64);
780 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
781 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
782 MachinePointerInfo(),
783 false, false, 0));
784 hasStructRetAttr = true;
785 continue;
786 }
787
788 if (VA.needsCustom()) {
789 assert(VA.getLocVT() == MVT::f64);
790
791 if (VA.isMemLoc()) {
792 unsigned Offset = VA.getLocMemOffset() + StackOffset;
793 // if it is double-word aligned, just store.
794 if (Offset % 8 == 0) {
795 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
796 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
797 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
798 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
799 MachinePointerInfo(),
800 false, false, 0));
801 continue;
802 }
803 }
804
805 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
806 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
807 Arg, StackPtr, MachinePointerInfo(),
808 false, false, 0);
809 // Sparc is big-endian, so the high part comes first.
810 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
811 MachinePointerInfo(), false, false, false, 0);
812 // Increment the pointer to the other half.
813 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
814 DAG.getIntPtrConstant(4));
815 // Load the low part.
816 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr,
817 MachinePointerInfo(), false, false, false, 0);
818
819 if (VA.isRegLoc()) {
820 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi));
821 assert(i+1 != e);
822 CCValAssign &NextVA = ArgLocs[++i];
823 if (NextVA.isRegLoc()) {
824 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo));
825 } else {
826 // Store the low part in stack.
827 unsigned Offset = NextVA.getLocMemOffset() + StackOffset;
828 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
829 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
830 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
831 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
832 MachinePointerInfo(),
833 false, false, 0));
834 }
835 } else {
836 unsigned Offset = VA.getLocMemOffset() + StackOffset;
837 // Store the high part.
838 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
839 SDValue PtrOff = DAG.getIntPtrConstant(Offset);
840 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
841 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff,
842 MachinePointerInfo(),
843 false, false, 0));
844 // Store the low part.
845 PtrOff = DAG.getIntPtrConstant(Offset+4);
846 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
847 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff,
848 MachinePointerInfo(),
849 false, false, 0));
850 }
851 continue;
852 }
853
854 // Arguments that can be passed on register must be kept at
855 // RegsToPass vector
856 if (VA.isRegLoc()) {
857 if (VA.getLocVT() != MVT::f32) {
858 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
859 continue;
860 }
861 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
862 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
863 continue;
864 }
865
866 assert(VA.isMemLoc());
867
868 // Create a store off the stack pointer for this argument.
869 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
870 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset);
871 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
872 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
873 MachinePointerInfo(),
874 false, false, 0));
875 }
876
877
878 // Emit all stores, make sure the occur before any copies into physregs.
879 if (!MemOpChains.empty())
880 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
881
882 // Build a sequence of copy-to-reg nodes chained together with token
883 // chain and flag operands which copy the outgoing args into registers.
884 // The InFlag in necessary since all emitted instructions must be
885 // stuck together.
886 SDValue InFlag;
887 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
888 unsigned Reg = toCallerWindow(RegsToPass[i].first);
889 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
890 InFlag = Chain.getValue(1);
891 }
892
893 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0;
894 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
895
896 // If the callee is a GlobalAddress node (quite common, every direct call is)
897 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
898 // Likewise ExternalSymbol -> TargetExternalSymbol.
899 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
900 ? SparcMCExpr::VK_Sparc_WPLT30 : 0);
901 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
902 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF);
903 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
904 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF);
905
906 // Returns a chain & a flag for retval copy to use
907 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
908 SmallVector<SDValue, 8> Ops;
909 Ops.push_back(Chain);
910 Ops.push_back(Callee);
911 if (hasStructRetAttr)
912 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32));
913 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
914 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first),
915 RegsToPass[i].second.getValueType()));
916
917 // Add a register mask operand representing the call-preserved registers.
918 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
919 const uint32_t *Mask =
920 ((hasReturnsTwice)
921 ? TRI->getRTCallPreservedMask(CallConv)
922 : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv));
923 assert(Mask && "Missing call preserved mask for calling convention");
924 Ops.push_back(DAG.getRegisterMask(Mask));
925
926 if (InFlag.getNode())
927 Ops.push_back(InFlag);
928
929 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops);
930 InFlag = Chain.getValue(1);
931
932 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
933 DAG.getIntPtrConstant(0, true), InFlag, dl);
934 InFlag = Chain.getValue(1);
935
936 // Assign locations to each value returned by this call.
937 SmallVector<CCValAssign, 16> RVLocs;
938 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
939 *DAG.getContext());
940
941 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
942
943 // Copy all of the result registers out of their specified physreg.
944 for (unsigned i = 0; i != RVLocs.size(); ++i) {
945 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()),
946 RVLocs[i].getValVT(), InFlag).getValue(1);
947 InFlag = Chain.getValue(2);
948 InVals.push_back(Chain.getValue(0));
949 }
950
951 return Chain;
952 }
953
954 // This functions returns true if CalleeName is a ABI function that returns
955 // a long double (fp128).
isFP128ABICall(const char * CalleeName)956 static bool isFP128ABICall(const char *CalleeName)
957 {
958 static const char *const ABICalls[] =
959 { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
960 "_Q_sqrt", "_Q_neg",
961 "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
962 "_Q_lltoq", "_Q_ulltoq",
963 nullptr
964 };
965 for (const char * const *I = ABICalls; *I != nullptr; ++I)
966 if (strcmp(CalleeName, *I) == 0)
967 return true;
968 return false;
969 }
970
971 unsigned
getSRetArgSize(SelectionDAG & DAG,SDValue Callee) const972 SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const
973 {
974 const Function *CalleeFn = nullptr;
975 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
976 CalleeFn = dyn_cast<Function>(G->getGlobal());
977 } else if (ExternalSymbolSDNode *E =
978 dyn_cast<ExternalSymbolSDNode>(Callee)) {
979 const Function *Fn = DAG.getMachineFunction().getFunction();
980 const Module *M = Fn->getParent();
981 const char *CalleeName = E->getSymbol();
982 CalleeFn = M->getFunction(CalleeName);
983 if (!CalleeFn && isFP128ABICall(CalleeName))
984 return 16; // Return sizeof(fp128)
985 }
986
987 if (!CalleeFn)
988 return 0;
989
990 assert(CalleeFn->hasStructRetAttr() &&
991 "Callee does not have the StructRet attribute.");
992
993 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType());
994 Type *ElementTy = Ty->getElementType();
995 return getDataLayout()->getTypeAllocSize(ElementTy);
996 }
997
998
999 // Fixup floating point arguments in the ... part of a varargs call.
1000 //
1001 // The SPARC v9 ABI requires that floating point arguments are treated the same
1002 // as integers when calling a varargs function. This does not apply to the
1003 // fixed arguments that are part of the function's prototype.
1004 //
1005 // This function post-processes a CCValAssign array created by
1006 // AnalyzeCallOperands().
fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> & ArgLocs,ArrayRef<ISD::OutputArg> Outs)1007 static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs,
1008 ArrayRef<ISD::OutputArg> Outs) {
1009 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1010 const CCValAssign &VA = ArgLocs[i];
1011 MVT ValTy = VA.getLocVT();
1012 // FIXME: What about f32 arguments? C promotes them to f64 when calling
1013 // varargs functions.
1014 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128))
1015 continue;
1016 // The fixed arguments to a varargs function still go in FP registers.
1017 if (Outs[VA.getValNo()].IsFixed)
1018 continue;
1019
1020 // This floating point argument should be reassigned.
1021 CCValAssign NewVA;
1022
1023 // Determine the offset into the argument array.
1024 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0;
1025 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16;
1026 unsigned Offset = argSize * (VA.getLocReg() - firstReg);
1027 assert(Offset < 16*8 && "Offset out of range, bad register enum?");
1028
1029 if (Offset < 6*8) {
1030 // This argument should go in %i0-%i5.
1031 unsigned IReg = SP::I0 + Offset/8;
1032 if (ValTy == MVT::f64)
1033 // Full register, just bitconvert into i64.
1034 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1035 IReg, MVT::i64, CCValAssign::BCvt);
1036 else {
1037 assert(ValTy == MVT::f128 && "Unexpected type!");
1038 // Full register, just bitconvert into i128 -- We will lower this into
1039 // two i64s in LowerCall_64.
1040 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(),
1041 IReg, MVT::i128, CCValAssign::BCvt);
1042 }
1043 } else {
1044 // This needs to go to memory, we're out of integer registers.
1045 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
1046 Offset, VA.getLocVT(), VA.getLocInfo());
1047 }
1048 ArgLocs[i] = NewVA;
1049 }
1050 }
1051
1052 // Lower a call for the 64-bit ABI.
1053 SDValue
LowerCall_64(TargetLowering::CallLoweringInfo & CLI,SmallVectorImpl<SDValue> & InVals) const1054 SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
1055 SmallVectorImpl<SDValue> &InVals) const {
1056 SelectionDAG &DAG = CLI.DAG;
1057 SDLoc DL = CLI.DL;
1058 SDValue Chain = CLI.Chain;
1059
1060 // Sparc target does not yet support tail call optimization.
1061 CLI.IsTailCall = false;
1062
1063 // Analyze operands of the call, assigning locations to each operand.
1064 SmallVector<CCValAssign, 16> ArgLocs;
1065 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), ArgLocs,
1066 *DAG.getContext());
1067 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64);
1068
1069 // Get the size of the outgoing arguments stack space requirement.
1070 // The stack offset computed by CC_Sparc64 includes all arguments.
1071 // Called functions expect 6 argument words to exist in the stack frame, used
1072 // or not.
1073 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset());
1074
1075 // Keep stack frames 16-byte aligned.
1076 ArgsSize = RoundUpToAlignment(ArgsSize, 16);
1077
1078 // Varargs calls require special treatment.
1079 if (CLI.IsVarArg)
1080 fixupVariableFloatArgs(ArgLocs, CLI.Outs);
1081
1082 // Adjust the stack pointer to make room for the arguments.
1083 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls
1084 // with more than 6 arguments.
1085 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1086 DL);
1087
1088 // Collect the set of registers to pass to the function and their values.
1089 // This will be emitted as a sequence of CopyToReg nodes glued to the call
1090 // instruction.
1091 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
1092
1093 // Collect chains from all the memory opeations that copy arguments to the
1094 // stack. They must follow the stack pointer adjustment above and precede the
1095 // call instruction itself.
1096 SmallVector<SDValue, 8> MemOpChains;
1097
1098 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1099 const CCValAssign &VA = ArgLocs[i];
1100 SDValue Arg = CLI.OutVals[i];
1101
1102 // Promote the value if needed.
1103 switch (VA.getLocInfo()) {
1104 default:
1105 llvm_unreachable("Unknown location info!");
1106 case CCValAssign::Full:
1107 break;
1108 case CCValAssign::SExt:
1109 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg);
1110 break;
1111 case CCValAssign::ZExt:
1112 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg);
1113 break;
1114 case CCValAssign::AExt:
1115 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg);
1116 break;
1117 case CCValAssign::BCvt:
1118 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But
1119 // SPARC does not support i128 natively. Lower it into two i64, see below.
1120 if (!VA.needsCustom() || VA.getValVT() != MVT::f128
1121 || VA.getLocVT() != MVT::i128)
1122 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1123 break;
1124 }
1125
1126 if (VA.isRegLoc()) {
1127 if (VA.needsCustom() && VA.getValVT() == MVT::f128
1128 && VA.getLocVT() == MVT::i128) {
1129 // Store and reload into the interger register reg and reg+1.
1130 unsigned Offset = 8 * (VA.getLocReg() - SP::I0);
1131 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128;
1132 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1133 SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset);
1134 HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
1135 HiPtrOff);
1136 SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8);
1137 LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr,
1138 LoPtrOff);
1139
1140 // Store to %sp+BIAS+128+Offset
1141 SDValue Store = DAG.getStore(Chain, DL, Arg, HiPtrOff,
1142 MachinePointerInfo(),
1143 false, false, 0);
1144 // Load into Reg and Reg+1
1145 SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff,
1146 MachinePointerInfo(),
1147 false, false, false, 0);
1148 SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff,
1149 MachinePointerInfo(),
1150 false, false, false, 0);
1151 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()),
1152 Hi64));
1153 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1),
1154 Lo64));
1155 continue;
1156 }
1157
1158 // The custom bit on an i32 return value indicates that it should be
1159 // passed in the high bits of the register.
1160 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) {
1161 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg,
1162 DAG.getConstant(32, MVT::i32));
1163
1164 // The next value may go in the low bits of the same register.
1165 // Handle both at once.
1166 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() &&
1167 ArgLocs[i+1].getLocReg() == VA.getLocReg()) {
1168 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64,
1169 CLI.OutVals[i+1]);
1170 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV);
1171 // Skip the next value, it's already done.
1172 ++i;
1173 }
1174 }
1175 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg));
1176 continue;
1177 }
1178
1179 assert(VA.isMemLoc());
1180
1181 // Create a store off the stack pointer for this argument.
1182 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy());
1183 // The argument area starts at %fp+BIAS+128 in the callee frame,
1184 // %sp+BIAS+128 in ours.
1185 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() +
1186 Subtarget->getStackPointerBias() +
1187 128);
1188 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff);
1189 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff,
1190 MachinePointerInfo(),
1191 false, false, 0));
1192 }
1193
1194 // Emit all stores, make sure they occur before the call.
1195 if (!MemOpChains.empty())
1196 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1197
1198 // Build a sequence of CopyToReg nodes glued together with token chain and
1199 // glue operands which copy the outgoing args into registers. The InGlue is
1200 // necessary since all emitted instructions must be stuck together in order
1201 // to pass the live physical registers.
1202 SDValue InGlue;
1203 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1204 Chain = DAG.getCopyToReg(Chain, DL,
1205 RegsToPass[i].first, RegsToPass[i].second, InGlue);
1206 InGlue = Chain.getValue(1);
1207 }
1208
1209 // If the callee is a GlobalAddress node (quite common, every direct call is)
1210 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1211 // Likewise ExternalSymbol -> TargetExternalSymbol.
1212 SDValue Callee = CLI.Callee;
1213 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS);
1214 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_)
1215 ? SparcMCExpr::VK_Sparc_WPLT30 : 0);
1216 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1217 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0,
1218 TF);
1219 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1220 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy(), TF);
1221
1222 // Build the operands for the call instruction itself.
1223 SmallVector<SDValue, 8> Ops;
1224 Ops.push_back(Chain);
1225 Ops.push_back(Callee);
1226 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1227 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1228 RegsToPass[i].second.getValueType()));
1229
1230 // Add a register mask operand representing the call-preserved registers.
1231 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo();
1232 const uint32_t *Mask =
1233 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv)
1234 : TRI->getCallPreservedMask(DAG.getMachineFunction(),
1235 CLI.CallConv));
1236 assert(Mask && "Missing call preserved mask for calling convention");
1237 Ops.push_back(DAG.getRegisterMask(Mask));
1238
1239 // Make sure the CopyToReg nodes are glued to the call instruction which
1240 // consumes the registers.
1241 if (InGlue.getNode())
1242 Ops.push_back(InGlue);
1243
1244 // Now the call itself.
1245 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1246 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, Ops);
1247 InGlue = Chain.getValue(1);
1248
1249 // Revert the stack pointer immediately after the call.
1250 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
1251 DAG.getIntPtrConstant(0, true), InGlue, DL);
1252 InGlue = Chain.getValue(1);
1253
1254 // Now extract the return values. This is more or less the same as
1255 // LowerFormalArguments_64.
1256
1257 // Assign locations to each value returned by this call.
1258 SmallVector<CCValAssign, 16> RVLocs;
1259 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), RVLocs,
1260 *DAG.getContext());
1261
1262 // Set inreg flag manually for codegen generated library calls that
1263 // return float.
1264 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == nullptr)
1265 CLI.Ins[0].Flags.setInReg();
1266
1267 RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64);
1268
1269 // Copy all of the result registers out of their specified physreg.
1270 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1271 CCValAssign &VA = RVLocs[i];
1272 unsigned Reg = toCallerWindow(VA.getLocReg());
1273
1274 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can
1275 // reside in the same register in the high and low bits. Reuse the
1276 // CopyFromReg previous node to avoid duplicate copies.
1277 SDValue RV;
1278 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1)))
1279 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
1280 RV = Chain.getValue(0);
1281
1282 // But usually we'll create a new CopyFromReg for a different register.
1283 if (!RV.getNode()) {
1284 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue);
1285 Chain = RV.getValue(1);
1286 InGlue = Chain.getValue(2);
1287 }
1288
1289 // Get the high bits for i32 struct elements.
1290 if (VA.getValVT() == MVT::i32 && VA.needsCustom())
1291 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV,
1292 DAG.getConstant(32, MVT::i32));
1293
1294 // The callee promoted the return value, so insert an Assert?ext SDNode so
1295 // we won't promote the value again in this function.
1296 switch (VA.getLocInfo()) {
1297 case CCValAssign::SExt:
1298 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV,
1299 DAG.getValueType(VA.getValVT()));
1300 break;
1301 case CCValAssign::ZExt:
1302 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV,
1303 DAG.getValueType(VA.getValVT()));
1304 break;
1305 default:
1306 break;
1307 }
1308
1309 // Truncate the register down to the return value type.
1310 if (VA.isExtInLoc())
1311 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV);
1312
1313 InVals.push_back(RV);
1314 }
1315
1316 return Chain;
1317 }
1318
1319 //===----------------------------------------------------------------------===//
1320 // TargetLowering Implementation
1321 //===----------------------------------------------------------------------===//
1322
1323 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1324 /// condition.
IntCondCCodeToICC(ISD::CondCode CC)1325 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
1326 switch (CC) {
1327 default: llvm_unreachable("Unknown integer condition code!");
1328 case ISD::SETEQ: return SPCC::ICC_E;
1329 case ISD::SETNE: return SPCC::ICC_NE;
1330 case ISD::SETLT: return SPCC::ICC_L;
1331 case ISD::SETGT: return SPCC::ICC_G;
1332 case ISD::SETLE: return SPCC::ICC_LE;
1333 case ISD::SETGE: return SPCC::ICC_GE;
1334 case ISD::SETULT: return SPCC::ICC_CS;
1335 case ISD::SETULE: return SPCC::ICC_LEU;
1336 case ISD::SETUGT: return SPCC::ICC_GU;
1337 case ISD::SETUGE: return SPCC::ICC_CC;
1338 }
1339 }
1340
1341 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1342 /// FCC condition.
FPCondCCodeToFCC(ISD::CondCode CC)1343 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
1344 switch (CC) {
1345 default: llvm_unreachable("Unknown fp condition code!");
1346 case ISD::SETEQ:
1347 case ISD::SETOEQ: return SPCC::FCC_E;
1348 case ISD::SETNE:
1349 case ISD::SETUNE: return SPCC::FCC_NE;
1350 case ISD::SETLT:
1351 case ISD::SETOLT: return SPCC::FCC_L;
1352 case ISD::SETGT:
1353 case ISD::SETOGT: return SPCC::FCC_G;
1354 case ISD::SETLE:
1355 case ISD::SETOLE: return SPCC::FCC_LE;
1356 case ISD::SETGE:
1357 case ISD::SETOGE: return SPCC::FCC_GE;
1358 case ISD::SETULT: return SPCC::FCC_UL;
1359 case ISD::SETULE: return SPCC::FCC_ULE;
1360 case ISD::SETUGT: return SPCC::FCC_UG;
1361 case ISD::SETUGE: return SPCC::FCC_UGE;
1362 case ISD::SETUO: return SPCC::FCC_U;
1363 case ISD::SETO: return SPCC::FCC_O;
1364 case ISD::SETONE: return SPCC::FCC_LG;
1365 case ISD::SETUEQ: return SPCC::FCC_UE;
1366 }
1367 }
1368
SparcTargetLowering(TargetMachine & TM,const SparcSubtarget & STI)1369 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM,
1370 const SparcSubtarget &STI)
1371 : TargetLowering(TM), Subtarget(&STI) {
1372 // Set up the register classes.
1373 addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
1374 addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
1375 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
1376 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
1377 if (Subtarget->is64Bit())
1378 addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
1379
1380 // Turn FP extload into load/fextend
1381 for (MVT VT : MVT::fp_valuetypes()) {
1382 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
1383 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand);
1384 }
1385
1386 // Sparc doesn't have i1 sign extending load
1387 for (MVT VT : MVT::integer_valuetypes())
1388 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
1389
1390 // Turn FP truncstore into trunc + store.
1391 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
1392 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
1393 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
1394
1395 // Custom legalize GlobalAddress nodes into LO/HI parts.
1396 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom);
1397 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom);
1398 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom);
1399 setOperationAction(ISD::BlockAddress, getPointerTy(), Custom);
1400
1401 // Sparc doesn't have sext_inreg, replace them with shl/sra
1402 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
1403 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
1404 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
1405
1406 // Sparc has no REM or DIVREM operations.
1407 setOperationAction(ISD::UREM, MVT::i32, Expand);
1408 setOperationAction(ISD::SREM, MVT::i32, Expand);
1409 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
1410 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
1411
1412 // ... nor does SparcV9.
1413 if (Subtarget->is64Bit()) {
1414 setOperationAction(ISD::UREM, MVT::i64, Expand);
1415 setOperationAction(ISD::SREM, MVT::i64, Expand);
1416 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
1417 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
1418 }
1419
1420 // Custom expand fp<->sint
1421 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
1422 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
1423 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
1424 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
1425
1426 // Custom Expand fp<->uint
1427 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
1428 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
1429 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
1430 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
1431
1432 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
1433 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
1434
1435 // Sparc has no select or setcc: expand to SELECT_CC.
1436 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1437 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1438 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1439 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1440
1441 setOperationAction(ISD::SETCC, MVT::i32, Expand);
1442 setOperationAction(ISD::SETCC, MVT::f32, Expand);
1443 setOperationAction(ISD::SETCC, MVT::f64, Expand);
1444 setOperationAction(ISD::SETCC, MVT::f128, Expand);
1445
1446 // Sparc doesn't have BRCOND either, it has BR_CC.
1447 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
1448 setOperationAction(ISD::BRIND, MVT::Other, Expand);
1449 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
1450 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
1451 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
1452 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
1453 setOperationAction(ISD::BR_CC, MVT::f128, Custom);
1454
1455 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
1456 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
1457 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
1458 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom);
1459
1460 if (Subtarget->is64Bit()) {
1461 setOperationAction(ISD::ADDC, MVT::i64, Custom);
1462 setOperationAction(ISD::ADDE, MVT::i64, Custom);
1463 setOperationAction(ISD::SUBC, MVT::i64, Custom);
1464 setOperationAction(ISD::SUBE, MVT::i64, Custom);
1465 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
1466 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
1467 setOperationAction(ISD::SELECT, MVT::i64, Expand);
1468 setOperationAction(ISD::SETCC, MVT::i64, Expand);
1469 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
1470 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
1471
1472 setOperationAction(ISD::CTPOP, MVT::i64,
1473 Subtarget->usePopc() ? Legal : Expand);
1474 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
1475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
1476 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
1477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
1478 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
1479 setOperationAction(ISD::ROTL , MVT::i64, Expand);
1480 setOperationAction(ISD::ROTR , MVT::i64, Expand);
1481 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
1482 }
1483
1484 // ATOMICs.
1485 // FIXME: We insert fences for each atomics and generate sub-optimal code
1486 // for PSO/TSO. Also, implement other atomicrmw operations.
1487
1488 setInsertFencesForAtomic(true);
1489
1490 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
1491 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32,
1492 (Subtarget->isV9() ? Legal: Expand));
1493
1494
1495 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
1496
1497 // Custom Lower Atomic LOAD/STORE
1498 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
1499 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
1500
1501 if (Subtarget->is64Bit()) {
1502 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
1503 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
1504 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
1505 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
1506 }
1507
1508 if (!Subtarget->isV9()) {
1509 // SparcV8 does not have FNEGD and FABSD.
1510 setOperationAction(ISD::FNEG, MVT::f64, Custom);
1511 setOperationAction(ISD::FABS, MVT::f64, Custom);
1512 }
1513
1514 setOperationAction(ISD::FSIN , MVT::f128, Expand);
1515 setOperationAction(ISD::FCOS , MVT::f128, Expand);
1516 setOperationAction(ISD::FSINCOS, MVT::f128, Expand);
1517 setOperationAction(ISD::FREM , MVT::f128, Expand);
1518 setOperationAction(ISD::FMA , MVT::f128, Expand);
1519 setOperationAction(ISD::FSIN , MVT::f64, Expand);
1520 setOperationAction(ISD::FCOS , MVT::f64, Expand);
1521 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
1522 setOperationAction(ISD::FREM , MVT::f64, Expand);
1523 setOperationAction(ISD::FMA , MVT::f64, Expand);
1524 setOperationAction(ISD::FSIN , MVT::f32, Expand);
1525 setOperationAction(ISD::FCOS , MVT::f32, Expand);
1526 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
1527 setOperationAction(ISD::FREM , MVT::f32, Expand);
1528 setOperationAction(ISD::FMA , MVT::f32, Expand);
1529 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
1531 setOperationAction(ISD::CTLZ , MVT::i32, Expand);
1532 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
1533 setOperationAction(ISD::ROTL , MVT::i32, Expand);
1534 setOperationAction(ISD::ROTR , MVT::i32, Expand);
1535 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
1536 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand);
1537 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
1538 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
1539 setOperationAction(ISD::FPOW , MVT::f128, Expand);
1540 setOperationAction(ISD::FPOW , MVT::f64, Expand);
1541 setOperationAction(ISD::FPOW , MVT::f32, Expand);
1542
1543 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
1544 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1545 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
1546
1547 // FIXME: Sparc provides these multiplies, but we don't have them yet.
1548 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
1549 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
1550
1551 if (Subtarget->is64Bit()) {
1552 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
1553 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
1554 setOperationAction(ISD::MULHU, MVT::i64, Expand);
1555 setOperationAction(ISD::MULHS, MVT::i64, Expand);
1556
1557 setOperationAction(ISD::UMULO, MVT::i64, Custom);
1558 setOperationAction(ISD::SMULO, MVT::i64, Custom);
1559
1560 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
1561 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
1562 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
1563 }
1564
1565 // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
1566 setOperationAction(ISD::VASTART , MVT::Other, Custom);
1567 // VAARG needs to be lowered to not do unaligned accesses for doubles.
1568 setOperationAction(ISD::VAARG , MVT::Other, Custom);
1569
1570 setOperationAction(ISD::TRAP , MVT::Other, Legal);
1571
1572 // Use the default implementation.
1573 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
1574 setOperationAction(ISD::VAEND , MVT::Other, Expand);
1575 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
1576 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
1577 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
1578
1579 setExceptionPointerRegister(SP::I0);
1580 setExceptionSelectorRegister(SP::I1);
1581
1582 setStackPointerRegisterToSaveRestore(SP::O6);
1583
1584 setOperationAction(ISD::CTPOP, MVT::i32,
1585 Subtarget->usePopc() ? Legal : Expand);
1586
1587 if (Subtarget->isV9() && Subtarget->hasHardQuad()) {
1588 setOperationAction(ISD::LOAD, MVT::f128, Legal);
1589 setOperationAction(ISD::STORE, MVT::f128, Legal);
1590 } else {
1591 setOperationAction(ISD::LOAD, MVT::f128, Custom);
1592 setOperationAction(ISD::STORE, MVT::f128, Custom);
1593 }
1594
1595 if (Subtarget->hasHardQuad()) {
1596 setOperationAction(ISD::FADD, MVT::f128, Legal);
1597 setOperationAction(ISD::FSUB, MVT::f128, Legal);
1598 setOperationAction(ISD::FMUL, MVT::f128, Legal);
1599 setOperationAction(ISD::FDIV, MVT::f128, Legal);
1600 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1601 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
1602 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
1603 if (Subtarget->isV9()) {
1604 setOperationAction(ISD::FNEG, MVT::f128, Legal);
1605 setOperationAction(ISD::FABS, MVT::f128, Legal);
1606 } else {
1607 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1608 setOperationAction(ISD::FABS, MVT::f128, Custom);
1609 }
1610
1611 if (!Subtarget->is64Bit()) {
1612 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1613 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1614 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1615 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1616 }
1617
1618 } else {
1619 // Custom legalize f128 operations.
1620
1621 setOperationAction(ISD::FADD, MVT::f128, Custom);
1622 setOperationAction(ISD::FSUB, MVT::f128, Custom);
1623 setOperationAction(ISD::FMUL, MVT::f128, Custom);
1624 setOperationAction(ISD::FDIV, MVT::f128, Custom);
1625 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1626 setOperationAction(ISD::FNEG, MVT::f128, Custom);
1627 setOperationAction(ISD::FABS, MVT::f128, Custom);
1628
1629 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
1630 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom);
1631 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
1632
1633 // Setup Runtime library names.
1634 if (Subtarget->is64Bit()) {
1635 setLibcallName(RTLIB::ADD_F128, "_Qp_add");
1636 setLibcallName(RTLIB::SUB_F128, "_Qp_sub");
1637 setLibcallName(RTLIB::MUL_F128, "_Qp_mul");
1638 setLibcallName(RTLIB::DIV_F128, "_Qp_div");
1639 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
1640 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
1641 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
1642 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
1643 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
1644 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
1645 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
1646 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
1647 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
1648 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
1649 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
1650 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
1651 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
1652 } else {
1653 setLibcallName(RTLIB::ADD_F128, "_Q_add");
1654 setLibcallName(RTLIB::SUB_F128, "_Q_sub");
1655 setLibcallName(RTLIB::MUL_F128, "_Q_mul");
1656 setLibcallName(RTLIB::DIV_F128, "_Q_div");
1657 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
1658 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
1659 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
1660 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
1661 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
1662 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
1663 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
1664 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
1665 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
1666 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
1667 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
1668 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
1669 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod");
1670 }
1671 }
1672
1673 setMinFunctionAlignment(2);
1674
1675 computeRegisterProperties(Subtarget->getRegisterInfo());
1676 }
1677
getTargetNodeName(unsigned Opcode) const1678 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
1679 switch (Opcode) {
1680 default: return nullptr;
1681 case SPISD::CMPICC: return "SPISD::CMPICC";
1682 case SPISD::CMPFCC: return "SPISD::CMPFCC";
1683 case SPISD::BRICC: return "SPISD::BRICC";
1684 case SPISD::BRXCC: return "SPISD::BRXCC";
1685 case SPISD::BRFCC: return "SPISD::BRFCC";
1686 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
1687 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC";
1688 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
1689 case SPISD::Hi: return "SPISD::Hi";
1690 case SPISD::Lo: return "SPISD::Lo";
1691 case SPISD::FTOI: return "SPISD::FTOI";
1692 case SPISD::ITOF: return "SPISD::ITOF";
1693 case SPISD::FTOX: return "SPISD::FTOX";
1694 case SPISD::XTOF: return "SPISD::XTOF";
1695 case SPISD::CALL: return "SPISD::CALL";
1696 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
1697 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
1698 case SPISD::FLUSHW: return "SPISD::FLUSHW";
1699 case SPISD::TLS_ADD: return "SPISD::TLS_ADD";
1700 case SPISD::TLS_LD: return "SPISD::TLS_LD";
1701 case SPISD::TLS_CALL: return "SPISD::TLS_CALL";
1702 }
1703 }
1704
getSetCCResultType(LLVMContext &,EVT VT) const1705 EVT SparcTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1706 if (!VT.isVector())
1707 return MVT::i32;
1708 return VT.changeVectorElementTypeToInteger();
1709 }
1710
1711 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
1712 /// be zero. Op is expected to be a target specific node. Used by DAG
1713 /// combiner.
computeKnownBitsForTargetNode(const SDValue Op,APInt & KnownZero,APInt & KnownOne,const SelectionDAG & DAG,unsigned Depth) const1714 void SparcTargetLowering::computeKnownBitsForTargetNode
1715 (const SDValue Op,
1716 APInt &KnownZero,
1717 APInt &KnownOne,
1718 const SelectionDAG &DAG,
1719 unsigned Depth) const {
1720 APInt KnownZero2, KnownOne2;
1721 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1722
1723 switch (Op.getOpcode()) {
1724 default: break;
1725 case SPISD::SELECT_ICC:
1726 case SPISD::SELECT_XCC:
1727 case SPISD::SELECT_FCC:
1728 DAG.computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
1729 DAG.computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
1730
1731 // Only known if known in both the LHS and RHS.
1732 KnownOne &= KnownOne2;
1733 KnownZero &= KnownZero2;
1734 break;
1735 }
1736 }
1737
1738 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
1739 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
LookThroughSetCC(SDValue & LHS,SDValue & RHS,ISD::CondCode CC,unsigned & SPCC)1740 static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
1741 ISD::CondCode CC, unsigned &SPCC) {
1742 if (isa<ConstantSDNode>(RHS) &&
1743 cast<ConstantSDNode>(RHS)->isNullValue() &&
1744 CC == ISD::SETNE &&
1745 (((LHS.getOpcode() == SPISD::SELECT_ICC ||
1746 LHS.getOpcode() == SPISD::SELECT_XCC) &&
1747 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
1748 (LHS.getOpcode() == SPISD::SELECT_FCC &&
1749 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
1750 isa<ConstantSDNode>(LHS.getOperand(0)) &&
1751 isa<ConstantSDNode>(LHS.getOperand(1)) &&
1752 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() &&
1753 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) {
1754 SDValue CMPCC = LHS.getOperand(3);
1755 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
1756 LHS = CMPCC.getOperand(0);
1757 RHS = CMPCC.getOperand(1);
1758 }
1759 }
1760
1761 // Convert to a target node and set target flags.
withTargetFlags(SDValue Op,unsigned TF,SelectionDAG & DAG) const1762 SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF,
1763 SelectionDAG &DAG) const {
1764 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op))
1765 return DAG.getTargetGlobalAddress(GA->getGlobal(),
1766 SDLoc(GA),
1767 GA->getValueType(0),
1768 GA->getOffset(), TF);
1769
1770 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op))
1771 return DAG.getTargetConstantPool(CP->getConstVal(),
1772 CP->getValueType(0),
1773 CP->getAlignment(),
1774 CP->getOffset(), TF);
1775
1776 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op))
1777 return DAG.getTargetBlockAddress(BA->getBlockAddress(),
1778 Op.getValueType(),
1779 0,
1780 TF);
1781
1782 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op))
1783 return DAG.getTargetExternalSymbol(ES->getSymbol(),
1784 ES->getValueType(0), TF);
1785
1786 llvm_unreachable("Unhandled address SDNode");
1787 }
1788
1789 // Split Op into high and low parts according to HiTF and LoTF.
1790 // Return an ADD node combining the parts.
makeHiLoPair(SDValue Op,unsigned HiTF,unsigned LoTF,SelectionDAG & DAG) const1791 SDValue SparcTargetLowering::makeHiLoPair(SDValue Op,
1792 unsigned HiTF, unsigned LoTF,
1793 SelectionDAG &DAG) const {
1794 SDLoc DL(Op);
1795 EVT VT = Op.getValueType();
1796 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG));
1797 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG));
1798 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1799 }
1800
1801 // Build SDNodes for producing an address from a GlobalAddress, ConstantPool,
1802 // or ExternalSymbol SDNode.
makeAddress(SDValue Op,SelectionDAG & DAG) const1803 SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
1804 SDLoc DL(Op);
1805 EVT VT = getPointerTy();
1806
1807 // Handle PIC mode first.
1808 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1809 // This is the pic32 code model, the GOT is known to be smaller than 4GB.
1810 SDValue HiLo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22,
1811 SparcMCExpr::VK_Sparc_GOT10, DAG);
1812 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT);
1813 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo);
1814 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1815 // function has calls.
1816 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1817 MFI->setHasCalls(true);
1818 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr,
1819 MachinePointerInfo::getGOT(), false, false, false, 0);
1820 }
1821
1822 // This is one of the absolute code models.
1823 switch(getTargetMachine().getCodeModel()) {
1824 default:
1825 llvm_unreachable("Unsupported absolute code model");
1826 case CodeModel::Small:
1827 // abs32.
1828 return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1829 SparcMCExpr::VK_Sparc_LO, DAG);
1830 case CodeModel::Medium: {
1831 // abs44.
1832 SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44,
1833 SparcMCExpr::VK_Sparc_M44, DAG);
1834 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32));
1835 SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG);
1836 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44);
1837 return DAG.getNode(ISD::ADD, DL, VT, H44, L44);
1838 }
1839 case CodeModel::Large: {
1840 // abs64.
1841 SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH,
1842 SparcMCExpr::VK_Sparc_HM, DAG);
1843 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32));
1844 SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI,
1845 SparcMCExpr::VK_Sparc_LO, DAG);
1846 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo);
1847 }
1848 }
1849 }
1850
LowerGlobalAddress(SDValue Op,SelectionDAG & DAG) const1851 SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
1852 SelectionDAG &DAG) const {
1853 return makeAddress(Op, DAG);
1854 }
1855
LowerConstantPool(SDValue Op,SelectionDAG & DAG) const1856 SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
1857 SelectionDAG &DAG) const {
1858 return makeAddress(Op, DAG);
1859 }
1860
LowerBlockAddress(SDValue Op,SelectionDAG & DAG) const1861 SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op,
1862 SelectionDAG &DAG) const {
1863 return makeAddress(Op, DAG);
1864 }
1865
LowerGlobalTLSAddress(SDValue Op,SelectionDAG & DAG) const1866 SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1867 SelectionDAG &DAG) const {
1868
1869 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1870 SDLoc DL(GA);
1871 const GlobalValue *GV = GA->getGlobal();
1872 EVT PtrVT = getPointerTy();
1873
1874 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1875
1876 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) {
1877 unsigned HiTF = ((model == TLSModel::GeneralDynamic)
1878 ? SparcMCExpr::VK_Sparc_TLS_GD_HI22
1879 : SparcMCExpr::VK_Sparc_TLS_LDM_HI22);
1880 unsigned LoTF = ((model == TLSModel::GeneralDynamic)
1881 ? SparcMCExpr::VK_Sparc_TLS_GD_LO10
1882 : SparcMCExpr::VK_Sparc_TLS_LDM_LO10);
1883 unsigned addTF = ((model == TLSModel::GeneralDynamic)
1884 ? SparcMCExpr::VK_Sparc_TLS_GD_ADD
1885 : SparcMCExpr::VK_Sparc_TLS_LDM_ADD);
1886 unsigned callTF = ((model == TLSModel::GeneralDynamic)
1887 ? SparcMCExpr::VK_Sparc_TLS_GD_CALL
1888 : SparcMCExpr::VK_Sparc_TLS_LDM_CALL);
1889
1890 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG);
1891 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1892 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo,
1893 withTargetFlags(Op, addTF, DAG));
1894
1895 SDValue Chain = DAG.getEntryNode();
1896 SDValue InFlag;
1897
1898 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL);
1899 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag);
1900 InFlag = Chain.getValue(1);
1901 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT);
1902 SDValue Symbol = withTargetFlags(Op, callTF, DAG);
1903
1904 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1905 SmallVector<SDValue, 4> Ops;
1906 Ops.push_back(Chain);
1907 Ops.push_back(Callee);
1908 Ops.push_back(Symbol);
1909 Ops.push_back(DAG.getRegister(SP::O0, PtrVT));
1910 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask(
1911 DAG.getMachineFunction(), CallingConv::C);
1912 assert(Mask && "Missing call preserved mask for calling convention");
1913 Ops.push_back(DAG.getRegisterMask(Mask));
1914 Ops.push_back(InFlag);
1915 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, Ops);
1916 InFlag = Chain.getValue(1);
1917 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true),
1918 DAG.getIntPtrConstant(0, true), InFlag, DL);
1919 InFlag = Chain.getValue(1);
1920 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag);
1921
1922 if (model != TLSModel::LocalDynamic)
1923 return Ret;
1924
1925 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1926 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG));
1927 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1928 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG));
1929 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1930 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo,
1931 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG));
1932 }
1933
1934 if (model == TLSModel::InitialExec) {
1935 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX
1936 : SparcMCExpr::VK_Sparc_TLS_IE_LD);
1937
1938 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT);
1939
1940 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this
1941 // function has calls.
1942 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1943 MFI->setHasCalls(true);
1944
1945 SDValue TGA = makeHiLoPair(Op,
1946 SparcMCExpr::VK_Sparc_TLS_IE_HI22,
1947 SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG);
1948 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA);
1949 SDValue Offset = DAG.getNode(SPISD::TLS_LD,
1950 DL, PtrVT, Ptr,
1951 withTargetFlags(Op, ldTF, DAG));
1952 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT,
1953 DAG.getRegister(SP::G7, PtrVT), Offset,
1954 withTargetFlags(Op,
1955 SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG));
1956 }
1957
1958 assert(model == TLSModel::LocalExec);
1959 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT,
1960 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG));
1961 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT,
1962 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG));
1963 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo);
1964
1965 return DAG.getNode(ISD::ADD, DL, PtrVT,
1966 DAG.getRegister(SP::G7, PtrVT), Offset);
1967 }
1968
1969 SDValue
LowerF128_LibCallArg(SDValue Chain,ArgListTy & Args,SDValue Arg,SDLoc DL,SelectionDAG & DAG) const1970 SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args,
1971 SDValue Arg, SDLoc DL,
1972 SelectionDAG &DAG) const {
1973 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1974 EVT ArgVT = Arg.getValueType();
1975 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
1976
1977 ArgListEntry Entry;
1978 Entry.Node = Arg;
1979 Entry.Ty = ArgTy;
1980
1981 if (ArgTy->isFP128Ty()) {
1982 // Create a stack object and pass the pointer to the library function.
1983 int FI = MFI->CreateStackObject(16, 8, false);
1984 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy());
1985 Chain = DAG.getStore(Chain,
1986 DL,
1987 Entry.Node,
1988 FIPtr,
1989 MachinePointerInfo(),
1990 false,
1991 false,
1992 8);
1993
1994 Entry.Node = FIPtr;
1995 Entry.Ty = PointerType::getUnqual(ArgTy);
1996 }
1997 Args.push_back(Entry);
1998 return Chain;
1999 }
2000
2001 SDValue
LowerF128Op(SDValue Op,SelectionDAG & DAG,const char * LibFuncName,unsigned numArgs) const2002 SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG,
2003 const char *LibFuncName,
2004 unsigned numArgs) const {
2005
2006 ArgListTy Args;
2007
2008 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2009
2010 SDValue Callee = DAG.getExternalSymbol(LibFuncName, getPointerTy());
2011 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext());
2012 Type *RetTyABI = RetTy;
2013 SDValue Chain = DAG.getEntryNode();
2014 SDValue RetPtr;
2015
2016 if (RetTy->isFP128Ty()) {
2017 // Create a Stack Object to receive the return value of type f128.
2018 ArgListEntry Entry;
2019 int RetFI = MFI->CreateStackObject(16, 8, false);
2020 RetPtr = DAG.getFrameIndex(RetFI, getPointerTy());
2021 Entry.Node = RetPtr;
2022 Entry.Ty = PointerType::getUnqual(RetTy);
2023 if (!Subtarget->is64Bit())
2024 Entry.isSRet = true;
2025 Entry.isReturned = false;
2026 Args.push_back(Entry);
2027 RetTyABI = Type::getVoidTy(*DAG.getContext());
2028 }
2029
2030 assert(Op->getNumOperands() >= numArgs && "Not enough operands!");
2031 for (unsigned i = 0, e = numArgs; i != e; ++i) {
2032 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG);
2033 }
2034 TargetLowering::CallLoweringInfo CLI(DAG);
2035 CLI.setDebugLoc(SDLoc(Op)).setChain(Chain)
2036 .setCallee(CallingConv::C, RetTyABI, Callee, std::move(Args), 0);
2037
2038 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2039
2040 // chain is in second result.
2041 if (RetTyABI == RetTy)
2042 return CallInfo.first;
2043
2044 assert (RetTy->isFP128Ty() && "Unexpected return type!");
2045
2046 Chain = CallInfo.second;
2047
2048 // Load RetPtr to get the return value.
2049 return DAG.getLoad(Op.getValueType(),
2050 SDLoc(Op),
2051 Chain,
2052 RetPtr,
2053 MachinePointerInfo(),
2054 false, false, false, 8);
2055 }
2056
2057 SDValue
LowerF128Compare(SDValue LHS,SDValue RHS,unsigned & SPCC,SDLoc DL,SelectionDAG & DAG) const2058 SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS,
2059 unsigned &SPCC,
2060 SDLoc DL,
2061 SelectionDAG &DAG) const {
2062
2063 const char *LibCall = nullptr;
2064 bool is64Bit = Subtarget->is64Bit();
2065 switch(SPCC) {
2066 default: llvm_unreachable("Unhandled conditional code!");
2067 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break;
2068 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break;
2069 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break;
2070 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break;
2071 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break;
2072 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break;
2073 case SPCC::FCC_UL :
2074 case SPCC::FCC_ULE:
2075 case SPCC::FCC_UG :
2076 case SPCC::FCC_UGE:
2077 case SPCC::FCC_U :
2078 case SPCC::FCC_O :
2079 case SPCC::FCC_LG :
2080 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break;
2081 }
2082
2083 SDValue Callee = DAG.getExternalSymbol(LibCall, getPointerTy());
2084 Type *RetTy = Type::getInt32Ty(*DAG.getContext());
2085 ArgListTy Args;
2086 SDValue Chain = DAG.getEntryNode();
2087 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG);
2088 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG);
2089
2090 TargetLowering::CallLoweringInfo CLI(DAG);
2091 CLI.setDebugLoc(DL).setChain(Chain)
2092 .setCallee(CallingConv::C, RetTy, Callee, std::move(Args), 0);
2093
2094 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
2095
2096 // result is in first, and chain is in second result.
2097 SDValue Result = CallInfo.first;
2098
2099 switch(SPCC) {
2100 default: {
2101 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2102 SPCC = SPCC::ICC_NE;
2103 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2104 }
2105 case SPCC::FCC_UL : {
2106 SDValue Mask = DAG.getTargetConstant(1, Result.getValueType());
2107 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2108 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2109 SPCC = SPCC::ICC_NE;
2110 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2111 }
2112 case SPCC::FCC_ULE: {
2113 SDValue RHS = DAG.getTargetConstant(2, Result.getValueType());
2114 SPCC = SPCC::ICC_NE;
2115 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2116 }
2117 case SPCC::FCC_UG : {
2118 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
2119 SPCC = SPCC::ICC_G;
2120 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2121 }
2122 case SPCC::FCC_UGE: {
2123 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType());
2124 SPCC = SPCC::ICC_NE;
2125 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2126 }
2127
2128 case SPCC::FCC_U : {
2129 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
2130 SPCC = SPCC::ICC_E;
2131 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2132 }
2133 case SPCC::FCC_O : {
2134 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType());
2135 SPCC = SPCC::ICC_NE;
2136 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2137 }
2138 case SPCC::FCC_LG : {
2139 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
2140 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2141 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2142 SPCC = SPCC::ICC_NE;
2143 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2144 }
2145 case SPCC::FCC_UE : {
2146 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType());
2147 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask);
2148 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType());
2149 SPCC = SPCC::ICC_E;
2150 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS);
2151 }
2152 }
2153 }
2154
2155 static SDValue
LowerF128_FPEXTEND(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2156 LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG,
2157 const SparcTargetLowering &TLI) {
2158
2159 if (Op.getOperand(0).getValueType() == MVT::f64)
2160 return TLI.LowerF128Op(Op, DAG,
2161 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1);
2162
2163 if (Op.getOperand(0).getValueType() == MVT::f32)
2164 return TLI.LowerF128Op(Op, DAG,
2165 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1);
2166
2167 llvm_unreachable("fpextend with non-float operand!");
2168 return SDValue();
2169 }
2170
2171 static SDValue
LowerF128_FPROUND(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2172 LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG,
2173 const SparcTargetLowering &TLI) {
2174 // FP_ROUND on f64 and f32 are legal.
2175 if (Op.getOperand(0).getValueType() != MVT::f128)
2176 return Op;
2177
2178 if (Op.getValueType() == MVT::f64)
2179 return TLI.LowerF128Op(Op, DAG,
2180 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1);
2181 if (Op.getValueType() == MVT::f32)
2182 return TLI.LowerF128Op(Op, DAG,
2183 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1);
2184
2185 llvm_unreachable("fpround to non-float!");
2186 return SDValue();
2187 }
2188
LowerFP_TO_SINT(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2189 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
2190 const SparcTargetLowering &TLI,
2191 bool hasHardQuad) {
2192 SDLoc dl(Op);
2193 EVT VT = Op.getValueType();
2194 assert(VT == MVT::i32 || VT == MVT::i64);
2195
2196 // Expand f128 operations to fp128 abi calls.
2197 if (Op.getOperand(0).getValueType() == MVT::f128
2198 && (!hasHardQuad || !TLI.isTypeLegal(VT))) {
2199 const char *libName = TLI.getLibcallName(VT == MVT::i32
2200 ? RTLIB::FPTOSINT_F128_I32
2201 : RTLIB::FPTOSINT_F128_I64);
2202 return TLI.LowerF128Op(Op, DAG, libName, 1);
2203 }
2204
2205 // Expand if the resulting type is illegal.
2206 if (!TLI.isTypeLegal(VT))
2207 return SDValue();
2208
2209 // Otherwise, Convert the fp value to integer in an FP register.
2210 if (VT == MVT::i32)
2211 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
2212 else
2213 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
2214
2215 return DAG.getNode(ISD::BITCAST, dl, VT, Op);
2216 }
2217
LowerSINT_TO_FP(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2218 static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2219 const SparcTargetLowering &TLI,
2220 bool hasHardQuad) {
2221 SDLoc dl(Op);
2222 EVT OpVT = Op.getOperand(0).getValueType();
2223 assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
2224
2225 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
2226
2227 // Expand f128 operations to fp128 ABI calls.
2228 if (Op.getValueType() == MVT::f128
2229 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
2230 const char *libName = TLI.getLibcallName(OpVT == MVT::i32
2231 ? RTLIB::SINTTOFP_I32_F128
2232 : RTLIB::SINTTOFP_I64_F128);
2233 return TLI.LowerF128Op(Op, DAG, libName, 1);
2234 }
2235
2236 // Expand if the operand type is illegal.
2237 if (!TLI.isTypeLegal(OpVT))
2238 return SDValue();
2239
2240 // Otherwise, Convert the int value to FP in an FP register.
2241 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
2242 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
2243 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
2244 }
2245
LowerFP_TO_UINT(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2246 static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
2247 const SparcTargetLowering &TLI,
2248 bool hasHardQuad) {
2249 SDLoc dl(Op);
2250 EVT VT = Op.getValueType();
2251
2252 // Expand if it does not involve f128 or the target has support for
2253 // quad floating point instructions and the resulting type is legal.
2254 if (Op.getOperand(0).getValueType() != MVT::f128 ||
2255 (hasHardQuad && TLI.isTypeLegal(VT)))
2256 return SDValue();
2257
2258 assert(VT == MVT::i32 || VT == MVT::i64);
2259
2260 return TLI.LowerF128Op(Op, DAG,
2261 TLI.getLibcallName(VT == MVT::i32
2262 ? RTLIB::FPTOUINT_F128_I32
2263 : RTLIB::FPTOUINT_F128_I64),
2264 1);
2265 }
2266
LowerUINT_TO_FP(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2267 static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
2268 const SparcTargetLowering &TLI,
2269 bool hasHardQuad) {
2270 SDLoc dl(Op);
2271 EVT OpVT = Op.getOperand(0).getValueType();
2272 assert(OpVT == MVT::i32 || OpVT == MVT::i64);
2273
2274 // Expand if it does not involve f128 or the target has support for
2275 // quad floating point instructions and the operand type is legal.
2276 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
2277 return SDValue();
2278
2279 return TLI.LowerF128Op(Op, DAG,
2280 TLI.getLibcallName(OpVT == MVT::i32
2281 ? RTLIB::UINTTOFP_I32_F128
2282 : RTLIB::UINTTOFP_I64_F128),
2283 1);
2284 }
2285
LowerBR_CC(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2286 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
2287 const SparcTargetLowering &TLI,
2288 bool hasHardQuad) {
2289 SDValue Chain = Op.getOperand(0);
2290 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2291 SDValue LHS = Op.getOperand(2);
2292 SDValue RHS = Op.getOperand(3);
2293 SDValue Dest = Op.getOperand(4);
2294 SDLoc dl(Op);
2295 unsigned Opc, SPCC = ~0U;
2296
2297 // If this is a br_cc of a "setcc", and if the setcc got lowered into
2298 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2299 LookThroughSetCC(LHS, RHS, CC, SPCC);
2300
2301 // Get the condition flag.
2302 SDValue CompareFlag;
2303 if (LHS.getValueType().isInteger()) {
2304 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2305 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2306 // 32-bit compares use the icc flags, 64-bit uses the xcc flags.
2307 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC;
2308 } else {
2309 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2310 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2311 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2312 Opc = SPISD::BRICC;
2313 } else {
2314 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2315 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2316 Opc = SPISD::BRFCC;
2317 }
2318 }
2319 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
2320 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2321 }
2322
LowerSELECT_CC(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,bool hasHardQuad)2323 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
2324 const SparcTargetLowering &TLI,
2325 bool hasHardQuad) {
2326 SDValue LHS = Op.getOperand(0);
2327 SDValue RHS = Op.getOperand(1);
2328 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2329 SDValue TrueVal = Op.getOperand(2);
2330 SDValue FalseVal = Op.getOperand(3);
2331 SDLoc dl(Op);
2332 unsigned Opc, SPCC = ~0U;
2333
2334 // If this is a select_cc of a "setcc", and if the setcc got lowered into
2335 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
2336 LookThroughSetCC(LHS, RHS, CC, SPCC);
2337
2338 SDValue CompareFlag;
2339 if (LHS.getValueType().isInteger()) {
2340 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS);
2341 Opc = LHS.getValueType() == MVT::i32 ?
2342 SPISD::SELECT_ICC : SPISD::SELECT_XCC;
2343 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
2344 } else {
2345 if (!hasHardQuad && LHS.getValueType() == MVT::f128) {
2346 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2347 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG);
2348 Opc = SPISD::SELECT_ICC;
2349 } else {
2350 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS);
2351 Opc = SPISD::SELECT_FCC;
2352 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
2353 }
2354 }
2355 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
2356 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
2357 }
2358
LowerVASTART(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2359 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
2360 const SparcTargetLowering &TLI) {
2361 MachineFunction &MF = DAG.getMachineFunction();
2362 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>();
2363
2364 // Need frame address to find the address of VarArgsFrameIndex.
2365 MF.getFrameInfo()->setFrameAddressIsTaken(true);
2366
2367 // vastart just stores the address of the VarArgsFrameIndex slot into the
2368 // memory location argument.
2369 SDLoc DL(Op);
2370 SDValue Offset =
2371 DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(),
2372 DAG.getRegister(SP::I6, TLI.getPointerTy()),
2373 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset()));
2374 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2375 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1),
2376 MachinePointerInfo(SV), false, false, 0);
2377 }
2378
LowerVAARG(SDValue Op,SelectionDAG & DAG)2379 static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
2380 SDNode *Node = Op.getNode();
2381 EVT VT = Node->getValueType(0);
2382 SDValue InChain = Node->getOperand(0);
2383 SDValue VAListPtr = Node->getOperand(1);
2384 EVT PtrVT = VAListPtr.getValueType();
2385 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2386 SDLoc DL(Node);
2387 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr,
2388 MachinePointerInfo(SV), false, false, false, 0);
2389 // Increment the pointer, VAList, to the next vaarg.
2390 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
2391 DAG.getIntPtrConstant(VT.getSizeInBits()/8));
2392 // Store the incremented VAList to the legalized pointer.
2393 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr,
2394 VAListPtr, MachinePointerInfo(SV), false, false, 0);
2395 // Load the actual argument out of the pointer VAList.
2396 // We can't count on greater alignment than the word size.
2397 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(),
2398 false, false, false,
2399 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8);
2400 }
2401
LowerDYNAMIC_STACKALLOC(SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget)2402 static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
2403 const SparcSubtarget *Subtarget) {
2404 SDValue Chain = Op.getOperand(0); // Legalize the chain.
2405 SDValue Size = Op.getOperand(1); // Legalize the size.
2406 EVT VT = Size->getValueType(0);
2407 SDLoc dl(Op);
2408
2409 unsigned SPReg = SP::O6;
2410 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
2411 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
2412 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain
2413
2414 // The resultant pointer is actually 16 words from the bottom of the stack,
2415 // to provide a register spill area.
2416 unsigned regSpillArea = Subtarget->is64Bit() ? 128 : 96;
2417 regSpillArea += Subtarget->getStackPointerBias();
2418
2419 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP,
2420 DAG.getConstant(regSpillArea, VT));
2421 SDValue Ops[2] = { NewVal, Chain };
2422 return DAG.getMergeValues(Ops, dl);
2423 }
2424
2425
getFLUSHW(SDValue Op,SelectionDAG & DAG)2426 static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
2427 SDLoc dl(Op);
2428 SDValue Chain = DAG.getNode(SPISD::FLUSHW,
2429 dl, MVT::Other, DAG.getEntryNode());
2430 return Chain;
2431 }
2432
getFRAMEADDR(uint64_t depth,SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget)2433 static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG,
2434 const SparcSubtarget *Subtarget) {
2435 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2436 MFI->setFrameAddressIsTaken(true);
2437
2438 EVT VT = Op.getValueType();
2439 SDLoc dl(Op);
2440 unsigned FrameReg = SP::I6;
2441 unsigned stackBias = Subtarget->getStackPointerBias();
2442
2443 SDValue FrameAddr;
2444
2445 if (depth == 0) {
2446 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2447 if (Subtarget->is64Bit())
2448 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2449 DAG.getIntPtrConstant(stackBias));
2450 return FrameAddr;
2451 }
2452
2453 // flush first to make sure the windowed registers' values are in stack
2454 SDValue Chain = getFLUSHW(Op, DAG);
2455 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
2456
2457 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56;
2458
2459 while (depth--) {
2460 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2461 DAG.getIntPtrConstant(Offset));
2462 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(),
2463 false, false, false, 0);
2464 }
2465 if (Subtarget->is64Bit())
2466 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr,
2467 DAG.getIntPtrConstant(stackBias));
2468 return FrameAddr;
2469 }
2470
2471
LowerFRAMEADDR(SDValue Op,SelectionDAG & DAG,const SparcSubtarget * Subtarget)2472 static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG,
2473 const SparcSubtarget *Subtarget) {
2474
2475 uint64_t depth = Op.getConstantOperandVal(0);
2476
2477 return getFRAMEADDR(depth, Op, DAG, Subtarget);
2478
2479 }
2480
LowerRETURNADDR(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI,const SparcSubtarget * Subtarget)2481 static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG,
2482 const SparcTargetLowering &TLI,
2483 const SparcSubtarget *Subtarget) {
2484 MachineFunction &MF = DAG.getMachineFunction();
2485 MachineFrameInfo *MFI = MF.getFrameInfo();
2486 MFI->setReturnAddressIsTaken(true);
2487
2488 if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG))
2489 return SDValue();
2490
2491 EVT VT = Op.getValueType();
2492 SDLoc dl(Op);
2493 uint64_t depth = Op.getConstantOperandVal(0);
2494
2495 SDValue RetAddr;
2496 if (depth == 0) {
2497 unsigned RetReg = MF.addLiveIn(SP::I7,
2498 TLI.getRegClassFor(TLI.getPointerTy()));
2499 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
2500 return RetAddr;
2501 }
2502
2503 // Need frame address to find return address of the caller.
2504 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget);
2505
2506 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60;
2507 SDValue Ptr = DAG.getNode(ISD::ADD,
2508 dl, VT,
2509 FrameAddr,
2510 DAG.getIntPtrConstant(Offset));
2511 RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr,
2512 MachinePointerInfo(), false, false, false, 0);
2513
2514 return RetAddr;
2515 }
2516
LowerF64Op(SDValue Op,SelectionDAG & DAG,unsigned opcode)2517 static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode)
2518 {
2519 SDLoc dl(Op);
2520
2521 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!");
2522 assert(opcode == ISD::FNEG || opcode == ISD::FABS);
2523
2524 // Lower fneg/fabs on f64 to fneg/fabs on f32.
2525 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd.
2526 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd.
2527
2528 SDValue SrcReg64 = Op.getOperand(0);
2529 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32,
2530 SrcReg64);
2531 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32,
2532 SrcReg64);
2533
2534 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32);
2535
2536 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2537 dl, MVT::f64), 0);
2538 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64,
2539 DstReg64, Hi32);
2540 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64,
2541 DstReg64, Lo32);
2542 return DstReg64;
2543 }
2544
2545 // Lower a f128 load into two f64 loads.
LowerF128Load(SDValue Op,SelectionDAG & DAG)2546 static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
2547 {
2548 SDLoc dl(Op);
2549 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode());
2550 assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF
2551 && "Unexpected node type");
2552
2553 unsigned alignment = LdNode->getAlignment();
2554 if (alignment > 8)
2555 alignment = 8;
2556
2557 SDValue Hi64 = DAG.getLoad(MVT::f64,
2558 dl,
2559 LdNode->getChain(),
2560 LdNode->getBasePtr(),
2561 LdNode->getPointerInfo(),
2562 false, false, false, alignment);
2563 EVT addrVT = LdNode->getBasePtr().getValueType();
2564 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2565 LdNode->getBasePtr(),
2566 DAG.getConstant(8, addrVT));
2567 SDValue Lo64 = DAG.getLoad(MVT::f64,
2568 dl,
2569 LdNode->getChain(),
2570 LoPtr,
2571 LdNode->getPointerInfo(),
2572 false, false, false, alignment);
2573
2574 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2575 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2576
2577 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2578 dl, MVT::f128);
2579 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2580 MVT::f128,
2581 SDValue(InFP128, 0),
2582 Hi64,
2583 SubRegEven);
2584 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
2585 MVT::f128,
2586 SDValue(InFP128, 0),
2587 Lo64,
2588 SubRegOdd);
2589 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1),
2590 SDValue(Lo64.getNode(), 1) };
2591 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2592 SDValue Ops[2] = {SDValue(InFP128,0), OutChain};
2593 return DAG.getMergeValues(Ops, dl);
2594 }
2595
2596 // Lower a f128 store into two f64 stores.
LowerF128Store(SDValue Op,SelectionDAG & DAG)2597 static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
2598 SDLoc dl(Op);
2599 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode());
2600 assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF
2601 && "Unexpected node type");
2602 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
2603 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
2604
2605 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2606 dl,
2607 MVT::f64,
2608 StNode->getValue(),
2609 SubRegEven);
2610 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG,
2611 dl,
2612 MVT::f64,
2613 StNode->getValue(),
2614 SubRegOdd);
2615
2616 unsigned alignment = StNode->getAlignment();
2617 if (alignment > 8)
2618 alignment = 8;
2619
2620 SDValue OutChains[2];
2621 OutChains[0] = DAG.getStore(StNode->getChain(),
2622 dl,
2623 SDValue(Hi64, 0),
2624 StNode->getBasePtr(),
2625 MachinePointerInfo(),
2626 false, false, alignment);
2627 EVT addrVT = StNode->getBasePtr().getValueType();
2628 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
2629 StNode->getBasePtr(),
2630 DAG.getConstant(8, addrVT));
2631 OutChains[1] = DAG.getStore(StNode->getChain(),
2632 dl,
2633 SDValue(Lo64, 0),
2634 LoPtr,
2635 MachinePointerInfo(),
2636 false, false, alignment);
2637 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
2638 }
2639
LowerFNEGorFABS(SDValue Op,SelectionDAG & DAG,bool isV9)2640 static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
2641 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS)
2642 && "invalid opcode");
2643
2644 if (Op.getValueType() == MVT::f64)
2645 return LowerF64Op(Op, DAG, Op.getOpcode());
2646 if (Op.getValueType() != MVT::f128)
2647 return Op;
2648
2649 // Lower fabs/fneg on f128 to fabs/fneg on f64
2650 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
2651
2652 SDLoc dl(Op);
2653 SDValue SrcReg128 = Op.getOperand(0);
2654 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64,
2655 SrcReg128);
2656 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64,
2657 SrcReg128);
2658 if (isV9)
2659 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
2660 else
2661 Hi64 = LowerF64Op(Hi64, DAG, Op.getOpcode());
2662
2663 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
2664 dl, MVT::f128), 0);
2665 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128,
2666 DstReg128, Hi64);
2667 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128,
2668 DstReg128, Lo64);
2669 return DstReg128;
2670 }
2671
LowerADDC_ADDE_SUBC_SUBE(SDValue Op,SelectionDAG & DAG)2672 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
2673
2674 if (Op.getValueType() != MVT::i64)
2675 return Op;
2676
2677 SDLoc dl(Op);
2678 SDValue Src1 = Op.getOperand(0);
2679 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2680 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,
2681 DAG.getConstant(32, MVT::i64));
2682 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi);
2683
2684 SDValue Src2 = Op.getOperand(1);
2685 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2);
2686 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
2687 DAG.getConstant(32, MVT::i64));
2688 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi);
2689
2690
2691 bool hasChain = false;
2692 unsigned hiOpc = Op.getOpcode();
2693 switch (Op.getOpcode()) {
2694 default: llvm_unreachable("Invalid opcode");
2695 case ISD::ADDC: hiOpc = ISD::ADDE; break;
2696 case ISD::ADDE: hasChain = true; break;
2697 case ISD::SUBC: hiOpc = ISD::SUBE; break;
2698 case ISD::SUBE: hasChain = true; break;
2699 }
2700 SDValue Lo;
2701 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue);
2702 if (hasChain) {
2703 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo,
2704 Op.getOperand(2));
2705 } else {
2706 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo);
2707 }
2708 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1));
2709 SDValue Carry = Hi.getValue(1);
2710
2711 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo);
2712 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi);
2713 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
2714 DAG.getConstant(32, MVT::i64));
2715
2716 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo);
2717 SDValue Ops[2] = { Dst, Carry };
2718 return DAG.getMergeValues(Ops, dl);
2719 }
2720
2721 // Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode()
2722 // in LegalizeDAG.cpp except the order of arguments to the library function.
LowerUMULO_SMULO(SDValue Op,SelectionDAG & DAG,const SparcTargetLowering & TLI)2723 static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG,
2724 const SparcTargetLowering &TLI)
2725 {
2726 unsigned opcode = Op.getOpcode();
2727 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode.");
2728
2729 bool isSigned = (opcode == ISD::SMULO);
2730 EVT VT = MVT::i64;
2731 EVT WideVT = MVT::i128;
2732 SDLoc dl(Op);
2733 SDValue LHS = Op.getOperand(0);
2734
2735 if (LHS.getValueType() != VT)
2736 return Op;
2737
2738 SDValue ShiftAmt = DAG.getConstant(63, VT);
2739
2740 SDValue RHS = Op.getOperand(1);
2741 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt);
2742 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt);
2743 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS };
2744
2745 SDValue MulResult = TLI.makeLibCall(DAG,
2746 RTLIB::MUL_I128, WideVT,
2747 Args, 4, isSigned, dl).first;
2748 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2749 MulResult, DAG.getIntPtrConstant(0));
2750 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT,
2751 MulResult, DAG.getIntPtrConstant(1));
2752 if (isSigned) {
2753 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt);
2754 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE);
2755 } else {
2756 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, VT),
2757 ISD::SETNE);
2758 }
2759 // MulResult is a node with an illegal type. Because such things are not
2760 // generally permitted during this phase of legalization, ensure that
2761 // nothing is left using the node. The above EXTRACT_ELEMENT nodes should have
2762 // been folded.
2763 assert(MulResult->use_empty() && "Illegally typed node still in use!");
2764
2765 SDValue Ops[2] = { BottomHalf, TopHalf } ;
2766 return DAG.getMergeValues(Ops, dl);
2767 }
2768
LowerATOMIC_LOAD_STORE(SDValue Op,SelectionDAG & DAG)2769 static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) {
2770 // Monotonic load/stores are legal.
2771 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
2772 return Op;
2773
2774 // Otherwise, expand with a fence.
2775 return SDValue();
2776 }
2777
2778
2779 SDValue SparcTargetLowering::
LowerOperation(SDValue Op,SelectionDAG & DAG) const2780 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
2781
2782 bool hasHardQuad = Subtarget->hasHardQuad();
2783 bool isV9 = Subtarget->isV9();
2784
2785 switch (Op.getOpcode()) {
2786 default: llvm_unreachable("Should not custom lower this!");
2787
2788 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this,
2789 Subtarget);
2790 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG,
2791 Subtarget);
2792 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2793 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2794 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2795 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2796 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this,
2797 hasHardQuad);
2798 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this,
2799 hasHardQuad);
2800 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this,
2801 hasHardQuad);
2802 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this,
2803 hasHardQuad);
2804 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this,
2805 hasHardQuad);
2806 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this,
2807 hasHardQuad);
2808 case ISD::VASTART: return LowerVASTART(Op, DAG, *this);
2809 case ISD::VAARG: return LowerVAARG(Op, DAG);
2810 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG,
2811 Subtarget);
2812
2813 case ISD::LOAD: return LowerF128Load(Op, DAG);
2814 case ISD::STORE: return LowerF128Store(Op, DAG);
2815 case ISD::FADD: return LowerF128Op(Op, DAG,
2816 getLibcallName(RTLIB::ADD_F128), 2);
2817 case ISD::FSUB: return LowerF128Op(Op, DAG,
2818 getLibcallName(RTLIB::SUB_F128), 2);
2819 case ISD::FMUL: return LowerF128Op(Op, DAG,
2820 getLibcallName(RTLIB::MUL_F128), 2);
2821 case ISD::FDIV: return LowerF128Op(Op, DAG,
2822 getLibcallName(RTLIB::DIV_F128), 2);
2823 case ISD::FSQRT: return LowerF128Op(Op, DAG,
2824 getLibcallName(RTLIB::SQRT_F128),1);
2825 case ISD::FABS:
2826 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9);
2827 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this);
2828 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this);
2829 case ISD::ADDC:
2830 case ISD::ADDE:
2831 case ISD::SUBC:
2832 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
2833 case ISD::UMULO:
2834 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this);
2835 case ISD::ATOMIC_LOAD:
2836 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG);
2837 }
2838 }
2839
2840 MachineBasicBlock *
EmitInstrWithCustomInserter(MachineInstr * MI,MachineBasicBlock * BB) const2841 SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2842 MachineBasicBlock *BB) const {
2843 switch (MI->getOpcode()) {
2844 default: llvm_unreachable("Unknown SELECT_CC!");
2845 case SP::SELECT_CC_Int_ICC:
2846 case SP::SELECT_CC_FP_ICC:
2847 case SP::SELECT_CC_DFP_ICC:
2848 case SP::SELECT_CC_QFP_ICC:
2849 return expandSelectCC(MI, BB, SP::BCOND);
2850 case SP::SELECT_CC_Int_FCC:
2851 case SP::SELECT_CC_FP_FCC:
2852 case SP::SELECT_CC_DFP_FCC:
2853 case SP::SELECT_CC_QFP_FCC:
2854 return expandSelectCC(MI, BB, SP::FBCOND);
2855
2856 case SP::ATOMIC_LOAD_ADD_32:
2857 return expandAtomicRMW(MI, BB, SP::ADDrr);
2858 case SP::ATOMIC_LOAD_ADD_64:
2859 return expandAtomicRMW(MI, BB, SP::ADDXrr);
2860 case SP::ATOMIC_LOAD_SUB_32:
2861 return expandAtomicRMW(MI, BB, SP::SUBrr);
2862 case SP::ATOMIC_LOAD_SUB_64:
2863 return expandAtomicRMW(MI, BB, SP::SUBXrr);
2864 case SP::ATOMIC_LOAD_AND_32:
2865 return expandAtomicRMW(MI, BB, SP::ANDrr);
2866 case SP::ATOMIC_LOAD_AND_64:
2867 return expandAtomicRMW(MI, BB, SP::ANDXrr);
2868 case SP::ATOMIC_LOAD_OR_32:
2869 return expandAtomicRMW(MI, BB, SP::ORrr);
2870 case SP::ATOMIC_LOAD_OR_64:
2871 return expandAtomicRMW(MI, BB, SP::ORXrr);
2872 case SP::ATOMIC_LOAD_XOR_32:
2873 return expandAtomicRMW(MI, BB, SP::XORrr);
2874 case SP::ATOMIC_LOAD_XOR_64:
2875 return expandAtomicRMW(MI, BB, SP::XORXrr);
2876 case SP::ATOMIC_LOAD_NAND_32:
2877 return expandAtomicRMW(MI, BB, SP::ANDrr);
2878 case SP::ATOMIC_LOAD_NAND_64:
2879 return expandAtomicRMW(MI, BB, SP::ANDXrr);
2880
2881 case SP::ATOMIC_SWAP_64:
2882 return expandAtomicRMW(MI, BB, 0);
2883
2884 case SP::ATOMIC_LOAD_MAX_32:
2885 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G);
2886 case SP::ATOMIC_LOAD_MAX_64:
2887 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G);
2888 case SP::ATOMIC_LOAD_MIN_32:
2889 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE);
2890 case SP::ATOMIC_LOAD_MIN_64:
2891 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE);
2892 case SP::ATOMIC_LOAD_UMAX_32:
2893 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU);
2894 case SP::ATOMIC_LOAD_UMAX_64:
2895 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU);
2896 case SP::ATOMIC_LOAD_UMIN_32:
2897 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU);
2898 case SP::ATOMIC_LOAD_UMIN_64:
2899 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU);
2900 }
2901 }
2902
2903 MachineBasicBlock*
expandSelectCC(MachineInstr * MI,MachineBasicBlock * BB,unsigned BROpcode) const2904 SparcTargetLowering::expandSelectCC(MachineInstr *MI,
2905 MachineBasicBlock *BB,
2906 unsigned BROpcode) const {
2907 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
2908 DebugLoc dl = MI->getDebugLoc();
2909 unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
2910
2911 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2912 // control-flow pattern. The incoming instruction knows the destination vreg
2913 // to set, the condition code register to branch on, the true/false values to
2914 // select between, and a branch opcode to use.
2915 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2916 MachineFunction::iterator It = BB;
2917 ++It;
2918
2919 // thisMBB:
2920 // ...
2921 // TrueVal = ...
2922 // [f]bCC copy1MBB
2923 // fallthrough --> copy0MBB
2924 MachineBasicBlock *thisMBB = BB;
2925 MachineFunction *F = BB->getParent();
2926 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2927 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2928 F->insert(It, copy0MBB);
2929 F->insert(It, sinkMBB);
2930
2931 // Transfer the remainder of BB and its successor edges to sinkMBB.
2932 sinkMBB->splice(sinkMBB->begin(), BB,
2933 std::next(MachineBasicBlock::iterator(MI)),
2934 BB->end());
2935 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
2936
2937 // Add the true and fallthrough blocks as its successors.
2938 BB->addSuccessor(copy0MBB);
2939 BB->addSuccessor(sinkMBB);
2940
2941 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
2942
2943 // copy0MBB:
2944 // %FalseValue = ...
2945 // # fallthrough to sinkMBB
2946 BB = copy0MBB;
2947
2948 // Update machine-CFG edges
2949 BB->addSuccessor(sinkMBB);
2950
2951 // sinkMBB:
2952 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2953 // ...
2954 BB = sinkMBB;
2955 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
2956 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
2957 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
2958
2959 MI->eraseFromParent(); // The pseudo instruction is gone now.
2960 return BB;
2961 }
2962
2963 MachineBasicBlock*
expandAtomicRMW(MachineInstr * MI,MachineBasicBlock * MBB,unsigned Opcode,unsigned CondCode) const2964 SparcTargetLowering::expandAtomicRMW(MachineInstr *MI,
2965 MachineBasicBlock *MBB,
2966 unsigned Opcode,
2967 unsigned CondCode) const {
2968 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
2969 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
2970 DebugLoc DL = MI->getDebugLoc();
2971
2972 // MI is an atomic read-modify-write instruction of the form:
2973 //
2974 // rd = atomicrmw<op> addr, rs2
2975 //
2976 // All three operands are registers.
2977 unsigned DestReg = MI->getOperand(0).getReg();
2978 unsigned AddrReg = MI->getOperand(1).getReg();
2979 unsigned Rs2Reg = MI->getOperand(2).getReg();
2980
2981 // SelectionDAG has already inserted memory barriers before and after MI, so
2982 // we simply have to implement the operatiuon in terms of compare-and-swap.
2983 //
2984 // %val0 = load %addr
2985 // loop:
2986 // %val = phi %val0, %dest
2987 // %upd = op %val, %rs2
2988 // %dest = cas %addr, %val, %upd
2989 // cmp %val, %dest
2990 // bne loop
2991 // done:
2992 //
2993 bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg));
2994 const TargetRegisterClass *ValueRC =
2995 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
2996 unsigned Val0Reg = MRI.createVirtualRegister(ValueRC);
2997
2998 BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg)
2999 .addReg(AddrReg).addImm(0);
3000
3001 // Split the basic block MBB before MI and insert the loop block in the hole.
3002 MachineFunction::iterator MFI = MBB;
3003 const BasicBlock *LLVM_BB = MBB->getBasicBlock();
3004 MachineFunction *MF = MBB->getParent();
3005 MachineBasicBlock *LoopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3006 MachineBasicBlock *DoneMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3007 ++MFI;
3008 MF->insert(MFI, LoopMBB);
3009 MF->insert(MFI, DoneMBB);
3010
3011 // Move MI and following instructions to DoneMBB.
3012 DoneMBB->splice(DoneMBB->begin(), MBB, MI, MBB->end());
3013 DoneMBB->transferSuccessorsAndUpdatePHIs(MBB);
3014
3015 // Connect the CFG again.
3016 MBB->addSuccessor(LoopMBB);
3017 LoopMBB->addSuccessor(LoopMBB);
3018 LoopMBB->addSuccessor(DoneMBB);
3019
3020 // Build the loop block.
3021 unsigned ValReg = MRI.createVirtualRegister(ValueRC);
3022 // Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP).
3023 unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg);
3024
3025 BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg)
3026 .addReg(Val0Reg).addMBB(MBB)
3027 .addReg(DestReg).addMBB(LoopMBB);
3028
3029 if (CondCode) {
3030 // This is one of the min/max operations. We need a CMPrr followed by a
3031 // MOVXCC/MOVICC.
3032 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg);
3033 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3034 .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode);
3035 } else if (Opcode) {
3036 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg)
3037 .addReg(ValReg).addReg(Rs2Reg);
3038 }
3039
3040 if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 ||
3041 MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) {
3042 unsigned TmpReg = UpdReg;
3043 UpdReg = MRI.createVirtualRegister(ValueRC);
3044 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1);
3045 }
3046
3047 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg)
3048 .addReg(AddrReg).addReg(ValReg).addReg(UpdReg)
3049 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
3050 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg);
3051 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND))
3052 .addMBB(LoopMBB).addImm(SPCC::ICC_NE);
3053
3054 MI->eraseFromParent();
3055 return DoneMBB;
3056 }
3057
3058 //===----------------------------------------------------------------------===//
3059 // Sparc Inline Assembly Support
3060 //===----------------------------------------------------------------------===//
3061
3062 /// getConstraintType - Given a constraint letter, return the type of
3063 /// constraint it is for this target.
3064 SparcTargetLowering::ConstraintType
getConstraintType(const std::string & Constraint) const3065 SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
3066 if (Constraint.size() == 1) {
3067 switch (Constraint[0]) {
3068 default: break;
3069 case 'r': return C_RegisterClass;
3070 case 'I': // SIMM13
3071 return C_Other;
3072 }
3073 }
3074
3075 return TargetLowering::getConstraintType(Constraint);
3076 }
3077
3078 TargetLowering::ConstraintWeight SparcTargetLowering::
getSingleConstraintMatchWeight(AsmOperandInfo & info,const char * constraint) const3079 getSingleConstraintMatchWeight(AsmOperandInfo &info,
3080 const char *constraint) const {
3081 ConstraintWeight weight = CW_Invalid;
3082 Value *CallOperandVal = info.CallOperandVal;
3083 // If we don't have a value, we can't do a match,
3084 // but allow it at the lowest weight.
3085 if (!CallOperandVal)
3086 return CW_Default;
3087
3088 // Look at the constraint type.
3089 switch (*constraint) {
3090 default:
3091 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
3092 break;
3093 case 'I': // SIMM13
3094 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
3095 if (isInt<13>(C->getSExtValue()))
3096 weight = CW_Constant;
3097 }
3098 break;
3099 }
3100 return weight;
3101 }
3102
3103 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3104 /// vector. If it is invalid, don't add anything to Ops.
3105 void SparcTargetLowering::
LowerAsmOperandForConstraint(SDValue Op,std::string & Constraint,std::vector<SDValue> & Ops,SelectionDAG & DAG) const3106 LowerAsmOperandForConstraint(SDValue Op,
3107 std::string &Constraint,
3108 std::vector<SDValue> &Ops,
3109 SelectionDAG &DAG) const {
3110 SDValue Result(nullptr, 0);
3111
3112 // Only support length 1 constraints for now.
3113 if (Constraint.length() > 1)
3114 return;
3115
3116 char ConstraintLetter = Constraint[0];
3117 switch (ConstraintLetter) {
3118 default: break;
3119 case 'I':
3120 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
3121 if (isInt<13>(C->getSExtValue())) {
3122 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());
3123 break;
3124 }
3125 return;
3126 }
3127 }
3128
3129 if (Result.getNode()) {
3130 Ops.push_back(Result);
3131 return;
3132 }
3133 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
3134 }
3135
3136 std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const TargetRegisterInfo * TRI,const std::string & Constraint,MVT VT) const3137 SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3138 const std::string &Constraint,
3139 MVT VT) const {
3140 if (Constraint.size() == 1) {
3141 switch (Constraint[0]) {
3142 case 'r':
3143 return std::make_pair(0U, &SP::IntRegsRegClass);
3144 }
3145 } else if (!Constraint.empty() && Constraint.size() <= 5
3146 && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
3147 // constraint = '{r<d>}'
3148 // Remove the braces from around the name.
3149 StringRef name(Constraint.data()+1, Constraint.size()-2);
3150 // Handle register aliases:
3151 // r0-r7 -> g0-g7
3152 // r8-r15 -> o0-o7
3153 // r16-r23 -> l0-l7
3154 // r24-r31 -> i0-i7
3155 uint64_t intVal = 0;
3156 if (name.substr(0, 1).equals("r")
3157 && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
3158 const char regTypes[] = { 'g', 'o', 'l', 'i' };
3159 char regType = regTypes[intVal/8];
3160 char regIdx = '0' + (intVal % 8);
3161 char tmp[] = { '{', regType, regIdx, '}', 0 };
3162 std::string newConstraint = std::string(tmp);
3163 return TargetLowering::getRegForInlineAsmConstraint(TRI, newConstraint,
3164 VT);
3165 }
3166 }
3167
3168 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3169 }
3170
3171 bool
isOffsetFoldingLegal(const GlobalAddressSDNode * GA) const3172 SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3173 // The Sparc target isn't yet aware of offsets.
3174 return false;
3175 }
3176
ReplaceNodeResults(SDNode * N,SmallVectorImpl<SDValue> & Results,SelectionDAG & DAG) const3177 void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
3178 SmallVectorImpl<SDValue>& Results,
3179 SelectionDAG &DAG) const {
3180
3181 SDLoc dl(N);
3182
3183 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
3184
3185 switch (N->getOpcode()) {
3186 default:
3187 llvm_unreachable("Do not know how to custom type legalize this operation!");
3188
3189 case ISD::FP_TO_SINT:
3190 case ISD::FP_TO_UINT:
3191 // Custom lower only if it involves f128 or i64.
3192 if (N->getOperand(0).getValueType() != MVT::f128
3193 || N->getValueType(0) != MVT::i64)
3194 return;
3195 libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
3196 ? RTLIB::FPTOSINT_F128_I64
3197 : RTLIB::FPTOUINT_F128_I64);
3198
3199 Results.push_back(LowerF128Op(SDValue(N, 0),
3200 DAG,
3201 getLibcallName(libCall),
3202 1));
3203 return;
3204
3205 case ISD::SINT_TO_FP:
3206 case ISD::UINT_TO_FP:
3207 // Custom lower only if it involves f128 or i64.
3208 if (N->getValueType(0) != MVT::f128
3209 || N->getOperand(0).getValueType() != MVT::i64)
3210 return;
3211
3212 libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
3213 ? RTLIB::SINTTOFP_I64_F128
3214 : RTLIB::UINTTOFP_I64_F128);
3215
3216 Results.push_back(LowerF128Op(SDValue(N, 0),
3217 DAG,
3218 getLibcallName(libCall),
3219 1));
3220 return;
3221 }
3222 }
3223