| /external/clang/test/CXX/temp/temp.spec/temp.expl.spec/ |
| D | p2.cpp | 18 namespace N0 { namespace
49 namespace N0 { namespace
86 namespace N0 { namespace
101 namespace N0 { namespace
112 namespace N0 { namespace
137 namespace N0 { namespace
176 namespace N0 { namespace
208 namespace N0 { namespace
|
| D | p2-0x.cpp | 20 namespace N0 { namespace
50 namespace N0 { namespace
87 namespace N0 { namespace
96 namespace N0 { namespace
140 namespace N0 { namespace
151 namespace N0 { namespace
176 namespace N0 { namespace
215 namespace N0 { namespace
247 namespace N0 { namespace
|
| /external/llvm/include/llvm/ADT/ |
| D | StringSwitch.h | 85 StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1], in Cases()
91 StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1], in Cases()
97 StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1], in Cases()
104 StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1], in Cases()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 687 SDValue N0, N1, N2; in isOneUseSetCC() local
768 SDValue N0, SDValue N1) { in ReassociateOps()
998 SDValue N0 = Op.getOperand(0); in PromoteIntBinOp() local
1056 SDValue N0 = Op.getOperand(0); in PromoteIntShiftOp() local
1441 SDValue N0 = N->getOperand(0); in combine() local
1576 SDValue N0 = N->getOperand(0); in visitADD() local
1749 SDValue N0 = N->getOperand(0); in visitADDC() local
1790 SDValue N0 = N->getOperand(0); in visitADDE() local
1821 SDValue N0 = N->getOperand(0); in visitSUB() local
1925 SDValue N0 = N->getOperand(0); in visitSUBC() local
[all …]
|
| /external/clang/test/CXX/basic/basic.lookup/basic.lookup.unqual/ |
| D | p3.cpp | 6 namespace N0 { namespace
|
| /external/clang/test/CXX/dcl.decl/dcl.meaning/dcl.fct.default/ |
| D | p4.cpp | 12 namespace N0 { namespace
|
| /external/ceres-solver/include/ceres/ |
| D | numeric_diff_functor.h | 125 N0, N1, N2, N3, N4, in functor_() argument
136 N0, N1, N2, N3, N4, in functor_() argument
|
| /external/clang/test/CXX/temp/temp.arg/temp.arg.type/ |
| D | p2.cpp | 22 namespace N0 { namespace
|
| /external/llvm/unittests/IR/ |
| D | MDBuilderTest.cpp | 85 MDNode *N0 = MDHelper.createTBAANode("Node", R); in TEST_F() local
|
| D | MetadataTest.cpp | 260 MDNode *N0 = getNode(); in TEST_F() local
319 MDNode *N0 = getNode(); in TEST_F() local
351 auto *N0 = MDNode::getDistinct(Context, None); in TEST_F() local
373 auto *N0 = MDNode::getDistinct(Context, None); in TEST_F() local
502 MDNode *N0 = MDNode::get(Context, None); in TEST_F() local
|
| /external/libopus/celt/ |
| D | rate.c | 150 int N0; in compute_pulse_cache() local
432 int N0, N, den; in interp_bits2pulses() local
|
| D | bands.c | 265 int N0; in anti_collapse() local
449 int i, c, N0; in spreading_decision() local
548 static void deinterleave_hadamard(celt_norm *X, int N0, int stride, int hadamard) in deinterleave_hadamard()
575 static void interleave_hadamard(celt_norm *X, int N0, int stride, int hadamard) in interleave_hadamard()
599 void haar1(celt_norm *X, int N0, int stride) in haar1()
1065 int N0=N; in quant_band() local
|
| D | vq.c | 137 int N0; in extract_collapse_mask() local
|
| D | celt_encoder.c | 549 int *tf_res, int lambda, celt_norm *X, int N0, int LM, in tf_analysis()
755 const opus_val16 *bandLogE, int end, int LM, int C, int N0, in alloc_trim_analysis()
858 int LM, int N0) in stereo_analysis()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 653 SDValue N0 = N.getOperand(0); in MatchWrapper() local
2166 SDValue N0 = Node->getOperand(0); in Select() local
2245 SDValue N0 = Node->getOperand(0); in Select() local
2263 SDValue N0 = Node->getOperand(0); in Select() local
2290 SDValue N0 = Node->getOperand(0); in Select() local
2440 SDValue N0 = Node->getOperand(0); in Select() local
2623 SDValue N0 = Node->getOperand(0); in Select() local
|
| /external/clang/test/SemaCXX/ |
| D | linkage-spec.cpp | 31 namespace N0 { namespace
|
| /external/bison/src/ |
| D | reduce.c | 67 useful_production (rule_number r, bitset N0) in useful_production()
|
| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelDAGToDAG.cpp | 827 SDValue N0 = Addr.getOperand(0); in SelectDS1Addr1Offset() local
863 SDValue N0 = Addr.getOperand(0); in SelectDS64Bit4ByteAligned() local
923 SDValue N0 = Addr.getOperand(0); in SelectMUBUF() local
955 SDValue N0 = Addr.getOperand(0); in SelectMUBUF() local
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelDAGToDAG.cpp | 141 SDValue N0 = N.getOperand(0); in MatchWrapper() local
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 613 SDValue N0 = Op.getOperand(0); in isADDADDMUL() local
1661 SDValue N0 = N->getOperand(0); in PerformDAGCombine() local
1698 SDValue N0 = N->getOperand(0); in PerformDAGCombine() local
1737 SDValue N0 = N->getOperand(0); in PerformDAGCombine() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 4183 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0)); in getCTPOP16BitCounts() local
4243 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16); in lowerCTPOP32BitElements() local
5860 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubSExt() local
5871 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubZExt() local
5885 SDNode *N0 = Op.getOperand(0).getNode(); in LowerMUL() local
5984 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) { in LowerSDIV_v4i16()
6026 SDValue N0 = Op.getOperand(0); in LowerSDIV() local
6061 SDValue N0 = Op.getOperand(0); in LowerUDIV() local
7737 SDValue N0 = N->getOperand(0); in combineSelectAndUseCommutative() local
7754 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, in AddCombineToVPADDL()
[all …]
|
| /external/clang/test/CodeGenCXX/ |
| D | bitfield.cpp | 9 namespace N0 { namespace
|
| /external/clang/test/SemaTemplate/ |
| D | instantiate-member-template.cpp | 120 namespace N0 { namespace
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelDAGToDAG.cpp | 1331 SDValue N0 = I->getOperand(0), N1 = I->getOperand(1); in PreprocessISelDAG() local
1376 SDValue N0 = N.getOperand(0); in SelectGlobalAddress() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 1830 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubSExt() local
1841 SDNode *N0 = N->getOperand(0).getNode(); in isAddSubZExt() local
1855 SDNode *N0 = Op.getOperand(0).getNode(); in LowerMUL() local
6888 SDValue N0 = N->getOperand(0); in performIntegerAbsCombine() local
6933 SDValue N0 = N->getOperand(0); in BuildSDIVPow2() local
7087 SDValue N0 = N->getOperand(0); in performIntToFpCombine() local
7182 SDValue N0 = N->getOperand(0); in tryCombineToBSL() local
7313 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); in performConcatVectorsCombine() local
8612 SDValue N0 = N->getOperand(0); in performVSelectCombine() local
8641 SDValue N0 = N->getOperand(0); in performSelectCombine() local
|