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Searched defs:Orders (Results 1 – 3 of 3) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp703 ProcessSDDbgValues(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, in ProcessSDDbgValues()
733 ProcessSourceNode(SDNode *N, SelectionDAG *DAG, InstrEmitter &Emitter, in ProcessSourceNode()
804 SmallVector<std::pair<unsigned, MachineInstr*>, 32> Orders; in EmitSchedule() local
/external/llvm/utils/TableGen/
DCodeGenRegisters.h270 std::vector<SmallVector<Record*, 16> > Orders; variable
/external/clang/lib/CodeGen/
DCGBuiltin.cpp1225 llvm::AtomicOrdering Orders[5] = { in EmitBuiltinExpr() local
1292 llvm::AtomicOrdering Orders[3] = { in EmitBuiltinExpr() local