1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file
11 /// \brief Interface definition of the TargetLowering class that is common
12 /// to all AMD GPUs.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
17 #define LLVM_LIB_TARGET_R600_AMDGPUISELLOWERING_H
18 
19 #include "llvm/Target/TargetLowering.h"
20 
21 namespace llvm {
22 
23 class AMDGPUMachineFunction;
24 class AMDGPUSubtarget;
25 class MachineRegisterInfo;
26 
27 class AMDGPUTargetLowering : public TargetLowering {
28 protected:
29   const AMDGPUSubtarget *Subtarget;
30 
31 private:
32   SDValue LowerConstantInitializer(const Constant* Init, const GlobalValue *GV,
33                                    const SDValue &InitPtr,
34                                    SDValue Chain,
35                                    SelectionDAG &DAG) const;
36   SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
38   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
39   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
40   /// \brief Lower vector stores by merging the vector elements into an integer
41   /// of the same bitwidth.
42   SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
43   /// \brief Split a vector store into multiple scalar stores.
44   /// \returns The resulting chain.
45 
46   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
47   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
48   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
49   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
50   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
51 
52   SDValue LowerFROUND32(SDValue Op, SelectionDAG &DAG) const;
53   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
54   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
55   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
56 
57   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
59   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
60 
61   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
62   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
63   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
64 
65   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
66 
67   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
68   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
69 
70 protected:
71   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
72   static EVT getEquivalentLoadRegType(LLVMContext &Context, EVT VT);
73 
74   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
75                                      SelectionDAG &DAG) const;
76 
77   /// \brief Split a vector load into a scalar load of each component.
78   SDValue ScalarizeVectorLoad(SDValue Op, SelectionDAG &DAG) const;
79 
80   /// \brief Split a vector load into 2 loads of half the vector.
81   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
82 
83   /// \brief Split a vector store into a scalar store of each component.
84   SDValue ScalarizeVectorStore(SDValue Op, SelectionDAG &DAG) const;
85 
86   /// \brief Split a vector store into 2 stores of half the vector.
87   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
88 
89   SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
90   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
91   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
92   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
93   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
94   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
95                                     SmallVectorImpl<SDValue> &Results) const;
96   bool isHWTrueValue(SDValue Op) const;
97   bool isHWFalseValue(SDValue Op) const;
98 
99   /// The SelectionDAGBuilder will automatically promote function arguments
100   /// with illegal types.  However, this does not work for the AMDGPU targets
101   /// since the function arguments are stored in memory as these illegal types.
102   /// In order to handle this properly we need to get the origianl types sizes
103   /// from the LLVM IR Function and fixup the ISD:InputArg values before
104   /// passing them to AnalyzeFormalArguments()
105   void getOriginalFunctionArgs(SelectionDAG &DAG,
106                                const Function *F,
107                                const SmallVectorImpl<ISD::InputArg> &Ins,
108                                SmallVectorImpl<ISD::InputArg> &OrigIns) const;
109   void AnalyzeFormalArguments(CCState &State,
110                               const SmallVectorImpl<ISD::InputArg> &Ins) const;
111 
112 public:
113   AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI);
114 
115   bool isFAbsFree(EVT VT) const override;
116   bool isFNegFree(EVT VT) const override;
117   bool isTruncateFree(EVT Src, EVT Dest) const override;
118   bool isTruncateFree(Type *Src, Type *Dest) const override;
119 
120   bool isZExtFree(Type *Src, Type *Dest) const override;
121   bool isZExtFree(EVT Src, EVT Dest) const override;
122   bool isZExtFree(SDValue Val, EVT VT2) const override;
123 
124   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
125 
126   MVT getVectorIdxTy() const override;
127   bool isSelectSupported(SelectSupportKind) const override;
128 
129   bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
130   bool ShouldShrinkFPConstant(EVT VT) const override;
131   bool shouldReduceLoadWidth(SDNode *Load,
132                              ISD::LoadExtType ExtType,
133                              EVT ExtVT) const override;
134 
135   bool isLoadBitCastBeneficial(EVT, EVT) const override;
136   bool isCheapToSpeculateCttz() const override;
137   bool isCheapToSpeculateCtlz() const override;
138 
139   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
140                       bool isVarArg,
141                       const SmallVectorImpl<ISD::OutputArg> &Outs,
142                       const SmallVectorImpl<SDValue> &OutVals,
143                       SDLoc DL, SelectionDAG &DAG) const override;
144   SDValue LowerCall(CallLoweringInfo &CLI,
145                     SmallVectorImpl<SDValue> &InVals) const override;
146 
147   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
148   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
149   void ReplaceNodeResults(SDNode * N,
150                           SmallVectorImpl<SDValue> &Results,
151                           SelectionDAG &DAG) const override;
152 
153   SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
154   SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
155   SDValue CombineFMinMaxLegacy(SDLoc DL,
156                                EVT VT,
157                                SDValue LHS,
158                                SDValue RHS,
159                                SDValue True,
160                                SDValue False,
161                                SDValue CC,
162                                DAGCombinerInfo &DCI) const;
163   SDValue CombineIMinMax(SDLoc DL,
164                          EVT VT,
165                          SDValue LHS,
166                          SDValue RHS,
167                          SDValue True,
168                          SDValue False,
169                          SDValue CC,
170                          SelectionDAG &DAG) const;
171 
172   const char* getTargetNodeName(unsigned Opcode) const override;
173 
174   SDValue getRsqrtEstimate(SDValue Operand,
175                            DAGCombinerInfo &DCI,
176                            unsigned &RefinementSteps,
177                            bool &UseOneConstNR) const override;
178   SDValue getRecipEstimate(SDValue Operand,
179                            DAGCombinerInfo &DCI,
180                            unsigned &RefinementSteps) const override;
181 
PostISelFolding(MachineSDNode * N,SelectionDAG & DAG)182   virtual SDNode *PostISelFolding(MachineSDNode *N,
183                                   SelectionDAG &DAG) const {
184     return N;
185   }
186 
187   /// \brief Determine which of the bits specified in \p Mask are known to be
188   /// either zero or one and return them in the \p KnownZero and \p KnownOne
189   /// bitsets.
190   void computeKnownBitsForTargetNode(const SDValue Op,
191                                      APInt &KnownZero,
192                                      APInt &KnownOne,
193                                      const SelectionDAG &DAG,
194                                      unsigned Depth = 0) const override;
195 
196   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
197                                            unsigned Depth = 0) const override;
198 
199   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
200   /// MachineFunction.
201   ///
202   /// \returns a RegisterSDNode representing Reg.
203   virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
204                                        const TargetRegisterClass *RC,
205                                        unsigned Reg, EVT VT) const;
206 };
207 
208 namespace AMDGPUISD {
209 
210 enum {
211   // AMDIL ISD Opcodes
212   FIRST_NUMBER = ISD::BUILTIN_OP_END,
213   CALL,        // Function call based on a single integer
214   UMUL,        // 32bit unsigned multiplication
215   RET_FLAG,
216   BRANCH_COND,
217   // End AMDIL ISD Opcodes
218   DWORDADDR,
219   FRACT,
220   CLAMP,
221 
222   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
223   // Denormals handled on some parts.
224   COS_HW,
225   SIN_HW,
226   FMAX_LEGACY,
227   SMAX,
228   UMAX,
229   FMIN_LEGACY,
230   SMIN,
231   UMIN,
232   FMAX3,
233   SMAX3,
234   UMAX3,
235   FMIN3,
236   SMIN3,
237   UMIN3,
238   URECIP,
239   DIV_SCALE,
240   DIV_FMAS,
241   DIV_FIXUP,
242   TRIG_PREOP, // 1 ULP max error for f64
243 
244   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
245   //            For f64, max error 2^29 ULP, handles denormals.
246   RCP,
247   RSQ,
248   RSQ_LEGACY,
249   RSQ_CLAMPED,
250   LDEXP,
251   FP_CLASS,
252   DOT4,
253   BFE_U32, // Extract range of bits with zero extension to 32-bits.
254   BFE_I32, // Extract range of bits with sign extension to 32-bits.
255   BFI, // (src0 & src1) | (~src0 & src2)
256   BFM, // Insert a range of bits into a 32-bit word.
257   BREV, // Reverse bits.
258   MUL_U24,
259   MUL_I24,
260   MAD_U24,
261   MAD_I24,
262   TEXTURE_FETCH,
263   EXPORT,
264   CONST_ADDRESS,
265   REGISTER_LOAD,
266   REGISTER_STORE,
267   LOAD_INPUT,
268   SAMPLE,
269   SAMPLEB,
270   SAMPLED,
271   SAMPLEL,
272 
273   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
274   CVT_F32_UBYTE0,
275   CVT_F32_UBYTE1,
276   CVT_F32_UBYTE2,
277   CVT_F32_UBYTE3,
278   /// This node is for VLIW targets and it is used to represent a vector
279   /// that is stored in consecutive registers with the same channel.
280   /// For example:
281   ///   |X  |Y|Z|W|
282   /// T0|v.x| | | |
283   /// T1|v.y| | | |
284   /// T2|v.z| | | |
285   /// T3|v.w| | | |
286   BUILD_VERTICAL_VECTOR,
287   /// Pointer to the start of the shader's constant data.
288   CONST_DATA_PTR,
289   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
290   STORE_MSKOR,
291   LOAD_CONSTANT,
292   TBUFFER_STORE_FORMAT,
293   LAST_AMDGPU_ISD_NUMBER
294 };
295 
296 
297 } // End namespace AMDGPUISD
298 
299 } // End namespace llvm
300 
301 #endif
302