1 /* libs/pixelflinger/codeflinger/MIPSAssembler.h 2 ** 3 ** Copyright 2012, The Android Open Source Project 4 ** 5 ** Licensed under the Apache License, Version 2.0 (the "License"); 6 ** you may not use this file except in compliance with the License. 7 ** You may obtain a copy of the License at 8 ** 9 ** http://www.apache.org/licenses/LICENSE-2.0 10 ** 11 ** Unless required by applicable law or agreed to in writing, software 12 ** distributed under the License is distributed on an "AS IS" BASIS, 13 ** WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 ** See the License for the specific language governing permissions and 15 ** limitations under the License. 16 */ 17 18 #ifndef ANDROID_MIPSASSEMBLER_H 19 #define ANDROID_MIPSASSEMBLER_H 20 21 #include <stdint.h> 22 #include <sys/types.h> 23 24 #include "tinyutils/KeyedVector.h" 25 #include "tinyutils/Vector.h" 26 #include "tinyutils/smartpointer.h" 27 28 #include "ARMAssemblerInterface.h" 29 #include "CodeCache.h" 30 31 namespace android { 32 33 class MIPSAssembler; // forward reference 34 35 // this class mimics ARMAssembler interface 36 // intent is to translate each ARM instruction to 1 or more MIPS instr 37 // implementation calls MIPSAssembler class to generate mips code 38 class ArmToMipsAssembler : public ARMAssemblerInterface 39 { 40 public: 41 ArmToMipsAssembler(const sp<Assembly>& assembly, 42 char *abuf = 0, int linesz = 0, int instr_count = 0); 43 virtual ~ArmToMipsAssembler(); 44 45 uint32_t* base() const; 46 uint32_t* pc() const; 47 void disassemble(const char* name); 48 49 virtual void reset(); 50 51 virtual int generate(const char* name); 52 virtual int getCodegenArch(); 53 54 virtual void prolog(); 55 virtual void epilog(uint32_t touched); 56 virtual void comment(const char* string); 57 58 59 // ----------------------------------------------------------------------- 60 // shifters and addressing modes 61 // ----------------------------------------------------------------------- 62 63 // shifters... 64 virtual bool isValidImmediate(uint32_t immed); 65 virtual int buildImmediate(uint32_t i, uint32_t& rot, uint32_t& imm); 66 67 virtual uint32_t imm(uint32_t immediate); 68 virtual uint32_t reg_imm(int Rm, int type, uint32_t shift); 69 virtual uint32_t reg_rrx(int Rm); 70 virtual uint32_t reg_reg(int Rm, int type, int Rs); 71 72 // addressing modes... 73 // LDR(B)/STR(B)/PLD 74 // (immediate and Rm can be negative, which indicates U=0) 75 virtual uint32_t immed12_pre(int32_t immed12, int W=0); 76 virtual uint32_t immed12_post(int32_t immed12); 77 virtual uint32_t reg_scale_pre(int Rm, int type=0, uint32_t shift=0, int W=0); 78 virtual uint32_t reg_scale_post(int Rm, int type=0, uint32_t shift=0); 79 80 // LDRH/LDRSB/LDRSH/STRH 81 // (immediate and Rm can be negative, which indicates U=0) 82 virtual uint32_t immed8_pre(int32_t immed8, int W=0); 83 virtual uint32_t immed8_post(int32_t immed8); 84 virtual uint32_t reg_pre(int Rm, int W=0); 85 virtual uint32_t reg_post(int Rm); 86 87 88 89 90 virtual void dataProcessing(int opcode, int cc, int s, 91 int Rd, int Rn, 92 uint32_t Op2); 93 virtual void MLA(int cc, int s, 94 int Rd, int Rm, int Rs, int Rn); 95 virtual void MUL(int cc, int s, 96 int Rd, int Rm, int Rs); 97 virtual void UMULL(int cc, int s, 98 int RdLo, int RdHi, int Rm, int Rs); 99 virtual void UMUAL(int cc, int s, 100 int RdLo, int RdHi, int Rm, int Rs); 101 virtual void SMULL(int cc, int s, 102 int RdLo, int RdHi, int Rm, int Rs); 103 virtual void SMUAL(int cc, int s, 104 int RdLo, int RdHi, int Rm, int Rs); 105 106 virtual void B(int cc, uint32_t* pc); 107 virtual void BL(int cc, uint32_t* pc); 108 virtual void BX(int cc, int Rn); 109 virtual void label(const char* theLabel); 110 virtual void B(int cc, const char* label); 111 virtual void BL(int cc, const char* label); 112 113 virtual uint32_t* pcForLabel(const char* label); 114 115 virtual void LDR (int cc, int Rd, 116 int Rn, uint32_t offset = 0); 117 virtual void LDRB(int cc, int Rd, 118 int Rn, uint32_t offset = 0); 119 virtual void STR (int cc, int Rd, 120 int Rn, uint32_t offset = 0); 121 virtual void STRB(int cc, int Rd, 122 int Rn, uint32_t offset = 0); 123 virtual void LDRH (int cc, int Rd, 124 int Rn, uint32_t offset = 0); 125 virtual void LDRSB(int cc, int Rd, 126 int Rn, uint32_t offset = 0); 127 virtual void LDRSH(int cc, int Rd, 128 int Rn, uint32_t offset = 0); 129 virtual void STRH (int cc, int Rd, 130 int Rn, uint32_t offset = 0); 131 132 virtual void LDM(int cc, int dir, 133 int Rn, int W, uint32_t reg_list); 134 virtual void STM(int cc, int dir, 135 int Rn, int W, uint32_t reg_list); 136 137 virtual void SWP(int cc, int Rn, int Rd, int Rm); 138 virtual void SWPB(int cc, int Rn, int Rd, int Rm); 139 virtual void SWI(int cc, uint32_t comment); 140 141 virtual void PLD(int Rn, uint32_t offset); 142 virtual void CLZ(int cc, int Rd, int Rm); 143 virtual void QADD(int cc, int Rd, int Rm, int Rn); 144 virtual void QDADD(int cc, int Rd, int Rm, int Rn); 145 virtual void QSUB(int cc, int Rd, int Rm, int Rn); 146 virtual void QDSUB(int cc, int Rd, int Rm, int Rn); 147 virtual void SMUL(int cc, int xy, 148 int Rd, int Rm, int Rs); 149 virtual void SMULW(int cc, int y, 150 int Rd, int Rm, int Rs); 151 virtual void SMLA(int cc, int xy, 152 int Rd, int Rm, int Rs, int Rn); 153 virtual void SMLAL(int cc, int xy, 154 int RdHi, int RdLo, int Rs, int Rm); 155 virtual void SMLAW(int cc, int y, 156 int Rd, int Rm, int Rs, int Rn); 157 158 // byte/half word extract... 159 virtual void UXTB16(int cc, int Rd, int Rm, int rotate); 160 161 // bit manipulation... 162 virtual void UBFX(int cc, int Rd, int Rn, int lsb, int width); 163 164 // this is some crap to share is MIPSAssembler class for debug 165 char * mArmDisassemblyBuffer; 166 int mArmLineLength; 167 int mArmInstrCount; 168 169 int mInum; // current arm instuction number (0..n) 170 uint32_t** mArmPC; // array: PC for 1st mips instr of 171 // each translated ARM instr 172 173 174 private: 175 ArmToMipsAssembler(const ArmToMipsAssembler& rhs); 176 ArmToMipsAssembler& operator = (const ArmToMipsAssembler& rhs); 177 178 void init_conditional_labels(void); 179 180 void protectConditionalOperands(int Rd); 181 182 // reg__tmp set to MIPS AT, reg 1 183 int dataProcAdrModes(int op, int& source, bool sign = false, int reg_tmp = 1); 184 185 sp<Assembly> mAssembly; 186 MIPSAssembler* mMips; 187 188 189 enum misc_constants_t { 190 ARM_MAX_INSTUCTIONS = 512 // based on ASSEMBLY_SCRATCH_SIZE 191 }; 192 193 enum { 194 SRC_REG = 0, 195 SRC_IMM, 196 SRC_ERROR = -1 197 }; 198 199 enum addr_modes { 200 // start above the range of legal mips reg #'s (0-31) 201 AMODE_REG = 0x20, 202 AMODE_IMM, AMODE_REG_IMM, // for data processing 203 AMODE_IMM_12_PRE, AMODE_IMM_12_POST, // for load/store 204 AMODE_REG_SCALE_PRE, AMODE_IMM_8_PRE, 205 AMODE_IMM_8_POST, AMODE_REG_PRE, 206 AMODE_UNSUPPORTED 207 }; 208 209 struct addr_mode_t { // address modes for current ARM instruction 210 int reg; 211 int stype; 212 uint32_t value; 213 bool writeback; // writeback the adr reg after modification 214 } amode; 215 216 enum cond_types { 217 CMP_COND = 1, 218 SBIT_COND 219 }; 220 221 struct cond_mode_t { // conditional-execution info for current ARM instruction 222 cond_types type; 223 int r1; 224 int r2; 225 int labelnum; 226 char label[100][10]; 227 } cond; 228 229 }; 230 231 232 233 234 // ---------------------------------------------------------------------------- 235 // ---------------------------------------------------------------------------- 236 // ---------------------------------------------------------------------------- 237 238 // This is the basic MIPS assembler, which just creates the opcodes in memory. 239 // All the more complicated work is done in ArmToMipsAssember above. 240 241 class MIPSAssembler 242 { 243 public: 244 MIPSAssembler(const sp<Assembly>& assembly, ArmToMipsAssembler *parent); 245 virtual ~MIPSAssembler(); 246 247 uint32_t* base() const; 248 uint32_t* pc() const; 249 void reset(); 250 251 void disassemble(const char* name); 252 253 void prolog(); 254 void epilog(uint32_t touched); 255 int generate(const char* name); 256 void comment(const char* string); 257 void label(const char* string); 258 259 // valid only after generate() has been called 260 uint32_t* pcForLabel(const char* label); 261 262 263 // ------------------------------------------------------------------------ 264 // MIPSAssemblerInterface... 265 // ------------------------------------------------------------------------ 266 267 #if 0 268 #pragma mark - 269 #pragma mark Arithmetic... 270 #endif 271 272 void ADDU(int Rd, int Rs, int Rt); 273 void ADDIU(int Rt, int Rs, int16_t imm); 274 void SUBU(int Rd, int Rs, int Rt); 275 void SUBIU(int Rt, int Rs, int16_t imm); 276 void NEGU(int Rd, int Rs); 277 void MUL(int Rd, int Rs, int Rt); 278 void MULT(int Rs, int Rt); // dest is hi,lo 279 void MULTU(int Rs, int Rt); // dest is hi,lo 280 void MADD(int Rs, int Rt); // hi,lo = hi,lo + Rs * Rt 281 void MADDU(int Rs, int Rt); // hi,lo = hi,lo + Rs * Rt 282 void MSUB(int Rs, int Rt); // hi,lo = hi,lo - Rs * Rt 283 void MSUBU(int Rs, int Rt); // hi,lo = hi,lo - Rs * Rt 284 void SEB(int Rd, int Rt); // sign-extend byte (mips32r2) 285 void SEH(int Rd, int Rt); // sign-extend half-word (mips32r2) 286 287 288 #if 0 289 #pragma mark - 290 #pragma mark Comparisons... 291 #endif 292 293 void SLT(int Rd, int Rs, int Rt); 294 void SLTI(int Rt, int Rs, int16_t imm); 295 void SLTU(int Rd, int Rs, int Rt); 296 void SLTIU(int Rt, int Rs, int16_t imm); 297 298 299 #if 0 300 #pragma mark - 301 #pragma mark Logical... 302 #endif 303 304 void AND(int Rd, int Rs, int Rt); 305 void ANDI(int Rd, int Rs, uint16_t imm); 306 void OR(int Rd, int Rs, int Rt); 307 void ORI(int Rt, int Rs, uint16_t imm); 308 void NOR(int Rd, int Rs, int Rt); 309 void NOT(int Rd, int Rs); 310 void XOR(int Rd, int Rs, int Rt); 311 void XORI(int Rt, int Rs, uint16_t imm); 312 313 void SLL(int Rd, int Rt, int shft); 314 void SLLV(int Rd, int Rt, int Rs); 315 void SRL(int Rd, int Rt, int shft); 316 void SRLV(int Rd, int Rt, int Rs); 317 void SRA(int Rd, int Rt, int shft); 318 void SRAV(int Rd, int Rt, int Rs); 319 void ROTR(int Rd, int Rt, int shft); // mips32r2 320 void ROTRV(int Rd, int Rt, int Rs); // mips32r2 321 void RORsyn(int Rd, int Rs, int Rt); // synthetic: d = s rotated by t 322 void RORIsyn(int Rd, int Rt, int rot); // synthetic: d = s rotated by immed 323 324 void CLO(int Rd, int Rs); 325 void CLZ(int Rd, int Rs); 326 void WSBH(int Rd, int Rt); 327 328 329 #if 0 330 #pragma mark - 331 #pragma mark Load/store... 332 #endif 333 334 void LW(int Rt, int Rbase, int16_t offset); 335 void SW(int Rt, int Rbase, int16_t offset); 336 void LB(int Rt, int Rbase, int16_t offset); 337 void LBU(int Rt, int Rbase, int16_t offset); 338 void SB(int Rt, int Rbase, int16_t offset); 339 void LH(int Rt, int Rbase, int16_t offset); 340 void LHU(int Rt, int Rbase, int16_t offset); 341 void SH(int Rt, int Rbase, int16_t offset); 342 void LUI(int Rt, int16_t offset); 343 344 #if 0 345 #pragma mark - 346 #pragma mark Register moves... 347 #endif 348 349 void MOVE(int Rd, int Rs); 350 void MOVN(int Rd, int Rs, int Rt); 351 void MOVZ(int Rd, int Rs, int Rt); 352 void MFHI(int Rd); 353 void MFLO(int Rd); 354 void MTHI(int Rs); 355 void MTLO(int Rs); 356 357 #if 0 358 #pragma mark - 359 #pragma mark Branch... 360 #endif 361 362 void B(const char* label); 363 void BEQ(int Rs, int Rt, const char* label); 364 void BNE(int Rs, int Rt, const char* label); 365 void BGEZ(int Rs, const char* label); 366 void BGTZ(int Rs, const char* label); 367 void BLEZ(int Rs, const char* label); 368 void BLTZ(int Rs, const char* label); 369 void JR(int Rs); 370 371 372 #if 0 373 #pragma mark - 374 #pragma mark Synthesized Branch... 375 #endif 376 377 // synthetic variants of above (using slt & friends) 378 void BEQZ(int Rs, const char* label); 379 void BNEZ(int Rs, const char* label); 380 void BGE(int Rs, int Rt, const char* label); 381 void BGEU(int Rs, int Rt, const char* label); 382 void BGT(int Rs, int Rt, const char* label); 383 void BGTU(int Rs, int Rt, const char* label); 384 void BLE(int Rs, int Rt, const char* label); 385 void BLEU(int Rs, int Rt, const char* label); 386 void BLT(int Rs, int Rt, const char* label); 387 void BLTU(int Rs, int Rt, const char* label); 388 389 #if 0 390 #pragma mark - 391 #pragma mark Misc... 392 #endif 393 394 void NOP(void); 395 void NOP2(void); 396 void UNIMPL(void); 397 398 399 400 401 402 private: 403 void string_detab(char *s); 404 void string_pad(char *s, int padded_len); 405 406 ArmToMipsAssembler *mParent; 407 sp<Assembly> mAssembly; 408 uint32_t* mBase; 409 uint32_t* mPC; 410 uint32_t* mPrologPC; 411 int64_t mDuration; 412 #if defined(WITH_LIB_HARDWARE) 413 bool mQemuTracing; 414 #endif 415 416 struct branch_target_t { branch_target_tbranch_target_t417 inline branch_target_t() : label(0), pc(0) { } branch_target_tbranch_target_t418 inline branch_target_t(const char* l, uint32_t* p) 419 : label(l), pc(p) { } 420 const char* label; 421 uint32_t* pc; 422 }; 423 424 Vector<branch_target_t> mBranchTargets; 425 KeyedVector< const char*, uint32_t* > mLabels; 426 KeyedVector< uint32_t*, const char* > mLabelsInverseMapping; 427 KeyedVector< uint32_t*, const char* > mComments; 428 429 430 431 432 // opcode field of all instructions 433 enum opcode_field { 434 spec_op, regimm_op, j_op, jal_op, // 00 435 beq_op, bne_op, blez_op, bgtz_op, 436 addi_op, addiu_op, slti_op, sltiu_op, // 08 437 andi_op, ori_op, xori_op, lui_op, 438 cop0_op, cop1_op, cop2_op, cop1x_op, // 10 439 beql_op, bnel_op, blezl_op, bgtzl_op, 440 daddi_op, daddiu_op, ldl_op, ldr_op, // 18 441 spec2_op, jalx_op, mdmx_op, spec3_op, 442 lb_op, lh_op, lwl_op, lw_op, // 20 443 lbu_op, lhu_op, lwr_op, lwu_op, 444 sb_op, sh_op, swl_op, sw_op, // 28 445 sdl_op, sdr_op, swr_op, cache_op, 446 ll_op, lwc1_op, lwc2_op, pref_op, // 30 447 lld_op, ldc1_op, ldc2_op, ld_op, 448 sc_op, swc1_op, swc2_op, rsrv_3b_op, // 38 449 scd_op, sdc1_op, sdc2_op, sd_op 450 }; 451 452 453 // func field for special opcode 454 enum func_spec_op { 455 sll_fn, movc_fn, srl_fn, sra_fn, // 00 456 sllv_fn, pmon_fn, srlv_fn, srav_fn, 457 jr_fn, jalr_fn, movz_fn, movn_fn, // 08 458 syscall_fn, break_fn, spim_fn, sync_fn, 459 mfhi_fn, mthi_fn, mflo_fn, mtlo_fn, // 10 460 dsllv_fn, rsrv_spec_2, dsrlv_fn, dsrav_fn, 461 mult_fn, multu_fn, div_fn, divu_fn, // 18 462 dmult_fn, dmultu_fn, ddiv_fn, ddivu_fn, 463 add_fn, addu_fn, sub_fn, subu_fn, // 20 464 and_fn, or_fn, xor_fn, nor_fn, 465 rsrv_spec_3, rsrv_spec_4, slt_fn, sltu_fn, // 28 466 dadd_fn, daddu_fn, dsub_fn, dsubu_fn, 467 tge_fn, tgeu_fn, tlt_fn, tltu_fn, // 30 468 teq_fn, rsrv_spec_5, tne_fn, rsrv_spec_6, 469 dsll_fn, rsrv_spec_7, dsrl_fn, dsra_fn, // 38 470 dsll32_fn, rsrv_spec_8, dsrl32_fn, dsra32_fn 471 }; 472 473 // func field for spec2 opcode 474 enum func_spec2_op { 475 madd_fn, maddu_fn, mul_fn, rsrv_spec2_3, 476 msub_fn, msubu_fn, 477 clz_fn = 0x20, clo_fn, 478 dclz_fn = 0x24, dclo_fn, 479 sdbbp_fn = 0x3f 480 }; 481 482 // func field for spec3 opcode 483 enum func_spec3_op { 484 ext_fn, dextm_fn, dextu_fn, dext_fn, 485 ins_fn, dinsm_fn, dinsu_fn, dins_fn, 486 bshfl_fn = 0x20, 487 dbshfl_fn = 0x24, 488 rdhwr_fn = 0x3b 489 }; 490 491 // sa field for spec3 opcodes, with BSHFL function 492 enum func_spec3_bshfl { 493 wsbh_fn = 0x02, 494 seb_fn = 0x10, 495 seh_fn = 0x18 496 }; 497 498 // rt field of regimm opcodes. 499 enum regimm_fn { 500 bltz_fn, bgez_fn, bltzl_fn, bgezl_fn, 501 rsrv_ri_fn4, rsrv_ri_fn5, rsrv_ri_fn6, rsrv_ri_fn7, 502 tgei_fn, tgeiu_fn, tlti_fn, tltiu_fn, 503 teqi_fn, rsrv_ri_fn_0d, tnei_fn, rsrv_ri_fn0f, 504 bltzal_fn, bgezal_fn, bltzall_fn, bgezall_fn, 505 bposge32_fn= 0x1c, 506 synci_fn = 0x1f 507 }; 508 509 510 // func field for mad opcodes (MIPS IV). 511 enum mad_func { 512 madd_fp_op = 0x08, msub_fp_op = 0x0a, 513 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e 514 }; 515 516 517 enum mips_inst_shifts { 518 OP_SHF = 26, 519 JTARGET_SHF = 0, 520 RS_SHF = 21, 521 RT_SHF = 16, 522 RD_SHF = 11, 523 RE_SHF = 6, 524 SA_SHF = RE_SHF, // synonym 525 IMM_SHF = 0, 526 FUNC_SHF = 0, 527 528 // mask values 529 MSK_16 = 0xffff, 530 531 532 CACHEOP_SHF = 18, 533 CACHESEL_SHF = 16, 534 }; 535 }; 536 537 enum mips_regnames { 538 R_zero = 0, 539 R_at, R_v0, R_v1, R_a0, R_a1, R_a2, R_a3, 540 R_t0, R_t1, R_t2, R_t3, R_t4, R_t5, R_t6, R_t7, 541 R_s0, R_s1, R_s2, R_s3, R_s4, R_s5, R_s6, R_s7, 542 R_t8, R_t9, R_k0, R_k1, R_gp, R_sp, R_s8, R_ra, 543 R_lr = R_s8, 544 545 // arm regs 0-15 are mips regs 2-17 (meaning s0 & s1 are used) 546 R_at2 = R_s2, // R_at2 = 18 = s2 547 R_cmp = R_s3, // R_cmp = 19 = s3 548 R_cmp2 = R_s4 // R_cmp2 = 20 = s4 549 }; 550 551 552 553 }; // namespace android 554 555 #endif //ANDROID_MIPSASSEMBLER_H 556