1 //===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // The LiveRangeEdit class represents changes done to a virtual register when it
11 // is spilled or split.
12 //
13 // The parent register is never changed. Instead, a number of new virtual
14 // registers are created and added to the newRegs vector.
15 //
16 //===----------------------------------------------------------------------===//
17 
18 #ifndef LLVM_CODEGEN_LIVERANGEEDIT_H
19 #define LLVM_CODEGEN_LIVERANGEEDIT_H
20 
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SetVector.h"
23 #include "llvm/ADT/SmallPtrSet.h"
24 #include "llvm/CodeGen/LiveInterval.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Target/TargetSubtargetInfo.h"
28 
29 namespace llvm {
30 
31 class AliasAnalysis;
32 class LiveIntervals;
33 class MachineBlockFrequencyInfo;
34 class MachineLoopInfo;
35 class VirtRegMap;
36 
37 class LiveRangeEdit : private MachineRegisterInfo::Delegate {
38 public:
39   /// Callback methods for LiveRangeEdit owners.
40   class Delegate {
41     virtual void anchor();
42   public:
43     /// Called immediately before erasing a dead machine instruction.
LRE_WillEraseInstruction(MachineInstr * MI)44     virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
45 
46     /// Called when a virtual register is no longer used. Return false to defer
47     /// its deletion from LiveIntervals.
LRE_CanEraseVirtReg(unsigned)48     virtual bool LRE_CanEraseVirtReg(unsigned) { return true; }
49 
50     /// Called before shrinking the live range of a virtual register.
LRE_WillShrinkVirtReg(unsigned)51     virtual void LRE_WillShrinkVirtReg(unsigned) {}
52 
53     /// Called after cloning a virtual register.
54     /// This is used for new registers representing connected components of Old.
LRE_DidCloneVirtReg(unsigned New,unsigned Old)55     virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {}
56 
~Delegate()57     virtual ~Delegate() {}
58   };
59 
60 private:
61   LiveInterval *Parent;
62   SmallVectorImpl<unsigned> &NewRegs;
63   MachineRegisterInfo &MRI;
64   LiveIntervals &LIS;
65   VirtRegMap *VRM;
66   const TargetInstrInfo &TII;
67   Delegate *const TheDelegate;
68 
69   /// FirstNew - Index of the first register added to NewRegs.
70   const unsigned FirstNew;
71 
72   /// ScannedRemattable - true when remattable values have been identified.
73   bool ScannedRemattable;
74 
75   /// Remattable - Values defined by remattable instructions as identified by
76   /// tii.isTriviallyReMaterializable().
77   SmallPtrSet<const VNInfo*,4> Remattable;
78 
79   /// Rematted - Values that were actually rematted, and so need to have their
80   /// live range trimmed or entirely removed.
81   SmallPtrSet<const VNInfo*,4> Rematted;
82 
83   /// scanRemattable - Identify the Parent values that may rematerialize.
84   void scanRemattable(AliasAnalysis *aa);
85 
86   /// allUsesAvailableAt - Return true if all registers used by OrigMI at
87   /// OrigIdx are also available with the same value at UseIdx.
88   bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
89                           SlotIndex UseIdx) const;
90 
91   /// foldAsLoad - If LI has a single use and a single def that can be folded as
92   /// a load, eliminate the register by folding the def into the use.
93   bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead);
94 
95   typedef SetVector<LiveInterval*,
96                     SmallVector<LiveInterval*, 8>,
97                     SmallPtrSet<LiveInterval*, 8> > ToShrinkSet;
98   /// Helper for eliminateDeadDefs.
99   void eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink);
100 
101   /// MachineRegisterInfo callback to notify when new virtual
102   /// registers are created.
103   void MRI_NoteNewVirtualRegister(unsigned VReg) override;
104 
105 public:
106   /// Create a LiveRangeEdit for breaking down parent into smaller pieces.
107   /// @param parent The register being spilled or split.
108   /// @param newRegs List to receive any new registers created. This needn't be
109   ///                empty initially, any existing registers are ignored.
110   /// @param MF The MachineFunction the live range edit is taking place in.
111   /// @param lis The collection of all live intervals in this function.
112   /// @param vrm Map of virtual registers to physical registers for this
113   ///            function.  If NULL, no virtual register map updates will
114   ///            be done.  This could be the case if called before Regalloc.
115   LiveRangeEdit(LiveInterval *parent, SmallVectorImpl<unsigned> &newRegs,
116                 MachineFunction &MF, LiveIntervals &lis, VirtRegMap *vrm,
117                 Delegate *delegate = nullptr)
Parent(parent)118       : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis),
119         VRM(vrm), TII(*MF.getSubtarget().getInstrInfo()),
120         TheDelegate(delegate), FirstNew(newRegs.size()),
121         ScannedRemattable(false) {
122     MRI.setDelegate(this);
123   }
124 
~LiveRangeEdit()125   ~LiveRangeEdit() override { MRI.resetDelegate(this); }
126 
getParent()127   LiveInterval &getParent() const {
128    assert(Parent && "No parent LiveInterval");
129    return *Parent;
130   }
getReg()131   unsigned getReg() const { return getParent().reg; }
132 
133   /// Iterator for accessing the new registers added by this edit.
134   typedef SmallVectorImpl<unsigned>::const_iterator iterator;
begin()135   iterator begin() const { return NewRegs.begin()+FirstNew; }
end()136   iterator end() const { return NewRegs.end(); }
size()137   unsigned size() const { return NewRegs.size()-FirstNew; }
empty()138   bool empty() const { return size() == 0; }
get(unsigned idx)139   unsigned get(unsigned idx) const { return NewRegs[idx+FirstNew]; }
140 
regs()141   ArrayRef<unsigned> regs() const {
142     return makeArrayRef(NewRegs).slice(FirstNew);
143   }
144 
145   /// createEmptyIntervalFrom - Create a new empty interval based on OldReg.
146   LiveInterval &createEmptyIntervalFrom(unsigned OldReg);
147 
148   /// createFrom - Create a new virtual register based on OldReg.
149   unsigned createFrom(unsigned OldReg);
150 
151   /// create - Create a new register with the same class and original slot as
152   /// parent.
createEmptyInterval()153   LiveInterval &createEmptyInterval() {
154     return createEmptyIntervalFrom(getReg());
155   }
156 
create()157   unsigned create() {
158     return createFrom(getReg());
159   }
160 
161   /// anyRematerializable - Return true if any parent values may be
162   /// rematerializable.
163   /// This function must be called before any rematerialization is attempted.
164   bool anyRematerializable(AliasAnalysis*);
165 
166   /// checkRematerializable - Manually add VNI to the list of rematerializable
167   /// values if DefMI may be rematerializable.
168   bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
169                              AliasAnalysis*);
170 
171   /// Remat - Information needed to rematerialize at a specific location.
172   struct Remat {
173     VNInfo *ParentVNI;      // parent_'s value at the remat location.
174     MachineInstr *OrigMI;   // Instruction defining ParentVNI.
RematRemat175     explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI), OrigMI(nullptr) {}
176   };
177 
178   /// canRematerializeAt - Determine if ParentVNI can be rematerialized at
179   /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
180   /// When cheapAsAMove is set, only cheap remats are allowed.
181   bool canRematerializeAt(Remat &RM,
182                           SlotIndex UseIdx,
183                           bool cheapAsAMove);
184 
185   /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an
186   /// instruction into MBB before MI. The new instruction is mapped, but
187   /// liveness is not updated.
188   /// Return the SlotIndex of the new instruction.
189   SlotIndex rematerializeAt(MachineBasicBlock &MBB,
190                             MachineBasicBlock::iterator MI,
191                             unsigned DestReg,
192                             const Remat &RM,
193                             const TargetRegisterInfo&,
194                             bool Late = false);
195 
196   /// markRematerialized - explicitly mark a value as rematerialized after doing
197   /// it manually.
markRematerialized(const VNInfo * ParentVNI)198   void markRematerialized(const VNInfo *ParentVNI) {
199     Rematted.insert(ParentVNI);
200   }
201 
202   /// didRematerialize - Return true if ParentVNI was rematerialized anywhere.
didRematerialize(const VNInfo * ParentVNI)203   bool didRematerialize(const VNInfo *ParentVNI) const {
204     return Rematted.count(ParentVNI);
205   }
206 
207   /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
208   /// to erase it from LIS.
209   void eraseVirtReg(unsigned Reg);
210 
211   /// eliminateDeadDefs - Try to delete machine instructions that are now dead
212   /// (allDefsAreDead returns true). This may cause live intervals to be trimmed
213   /// and further dead efs to be eliminated.
214   /// RegsBeingSpilled lists registers currently being spilled by the register
215   /// allocator.  These registers should not be split into new intervals
216   /// as currently those new intervals are not guaranteed to spill.
217   void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
218                          ArrayRef<unsigned> RegsBeingSpilled = None);
219 
220   /// calculateRegClassAndHint - Recompute register class and hint for each new
221   /// register.
222   void calculateRegClassAndHint(MachineFunction&,
223                                 const MachineLoopInfo&,
224                                 const MachineBlockFrequencyInfo&);
225 };
226 
227 }
228 
229 #endif
230