1 //===-- MSP430InstrInfo.h - MSP430 Instruction Information ------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MSP430 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
15 #define LLVM_LIB_TARGET_MSP430_MSP430INSTRINFO_H
16 
17 #include "MSP430RegisterInfo.h"
18 #include "llvm/Target/TargetInstrInfo.h"
19 
20 #define GET_INSTRINFO_HEADER
21 #include "MSP430GenInstrInfo.inc"
22 
23 namespace llvm {
24 
25 class MSP430Subtarget;
26 
27 /// MSP430II - This namespace holds all of the target specific flags that
28 /// instruction info tracks.
29 ///
30 namespace MSP430II {
31   enum {
32     SizeShift   = 2,
33     SizeMask    = 7 << SizeShift,
34 
35     SizeUnknown = 0 << SizeShift,
36     SizeSpecial = 1 << SizeShift,
37     Size2Bytes  = 2 << SizeShift,
38     Size4Bytes  = 3 << SizeShift,
39     Size6Bytes  = 4 << SizeShift
40   };
41 }
42 
43 class MSP430InstrInfo : public MSP430GenInstrInfo {
44   const MSP430RegisterInfo RI;
45   virtual void anchor();
46 public:
47   explicit MSP430InstrInfo(MSP430Subtarget &STI);
48 
49   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
50   /// such, whenever a client has an instance of instruction info, it should
51   /// always be able to get register info as well (through this method).
52   ///
getRegisterInfo()53   const TargetRegisterInfo &getRegisterInfo() const { return RI; }
54 
55   void copyPhysReg(MachineBasicBlock &MBB,
56                    MachineBasicBlock::iterator I, DebugLoc DL,
57                    unsigned DestReg, unsigned SrcReg,
58                    bool KillSrc) const override;
59 
60   void storeRegToStackSlot(MachineBasicBlock &MBB,
61                            MachineBasicBlock::iterator MI,
62                            unsigned SrcReg, bool isKill,
63                            int FrameIndex,
64                            const TargetRegisterClass *RC,
65                            const TargetRegisterInfo *TRI) const override;
66   void loadRegFromStackSlot(MachineBasicBlock &MBB,
67                             MachineBasicBlock::iterator MI,
68                             unsigned DestReg, int FrameIdx,
69                             const TargetRegisterClass *RC,
70                             const TargetRegisterInfo *TRI) const override;
71 
72   unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
73 
74   // Branch folding goodness
75   bool
76   ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
77   bool isUnpredicatedTerminator(const MachineInstr *MI) const override;
78   bool AnalyzeBranch(MachineBasicBlock &MBB,
79                      MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
80                      SmallVectorImpl<MachineOperand> &Cond,
81                      bool AllowModify) const override;
82 
83   unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
84   unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
85                         MachineBasicBlock *FBB,
86                         const SmallVectorImpl<MachineOperand> &Cond,
87                         DebugLoc DL) const override;
88 
89 };
90 
91 }
92 
93 #endif
94